3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
8 architecture behaviour of r_w_ram_be is
10 type word_t is array (0 to 3) of std_logic_vector(7 downto 0);
11 type ram_t is array (0 to (2**ADDR_WIDTH)-1) of word_t;
12 signal ram : ram_t := (others => ((x"00"), (x"00"), (x"00"), (x"00")));
13 signal q_local : word_t;
15 begin -- Re-organize the read data from the RAM to match the output
16 unpack: for i in 0 to 3 generate
17 q(8*(i+1) - 1 downto 8*i) <= q_local(i);
22 if(rising_edge(clk)) then
25 ram(to_integer(UNSIGNED(waddr)))(0) <= wdata(7 downto 0);
28 ram(to_integer(UNSIGNED(waddr)))(1) <= wdata(15 downto 8);
31 ram(to_integer(UNSIGNED(waddr)))(2) <= wdata(23 downto 16);
34 ram(to_integer(UNSIGNED(waddr)))(3) <= wdata(31 downto 24);
37 q_local <= ram(to_integer(UNSIGNED(raddr)));
41 end architecture behaviour;