3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
8 architecture behaviour of r2_w_ram is
10 subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
11 type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
13 signal ram : RAM_TYPE := (
18 others=> (others => '0'));
23 if rising_edge(clk) then
24 data_out1 <= ram(to_integer(UNSIGNED(rd_addr1)));
25 data_out2 <= ram(to_integer(UNSIGNED(rd_addr2)));
28 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
32 end architecture behaviour;