2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
7 use work.extension_pkg.all;
8 -------------------------------------------------------------------------------
10 -------------------------------------------------------------------------------
16 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 architecture behavior of pipeline_tb is
21 constant cc : time := 30 ns; -- test clock period
23 signal sys_clk_pin : std_logic;
24 signal sys_res_n_pin : std_logic;
27 signal dummy : std_logic;
29 signal jump_result_pin : instruction_addr_t;
30 signal prediction_result_pin : instruction_addr_t;
31 signal branch_prediction_bit_pin : std_logic;
32 signal alu_jump_bit_pin : std_logic;
33 signal instruction_pin : instruction_word_t;
34 signal prog_cnt : instruction_addr_t;
36 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
37 signal reg_wr_data_pin : gp_register_t;
38 signal reg_we_pin : std_logic;
39 signal to_next_stage_pin : dec_op;
41 signal result_pin : gp_register_t;--reg
42 signal result_addr_pin : gp_addr_t;--reg
43 signal addr_pin : word_t; --memaddr
44 signal data_pin : gp_register_t; --mem data --ureg
45 signal alu_jump_pin : std_logic;--reg
46 signal brpr_pin : std_logic; --reg
47 signal wr_en_pin : std_logic;--regop --reg
48 signal dmem_pin : std_logic;--memop
49 signal dmem_wr_en_pin : std_logic;
50 signal hword_pin : std_logic;
51 signal byte_s_pin, tx_pin : std_logic;
53 signal gpm_in_pin : extmod_rec;
54 signal gpm_out_pin : gp_register_t;
55 signal nop_pin : std_logic;
57 signal cycle_cnt : integer;
59 signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
64 -- instruction_ram : r_w_ram
66 -- PHYS_INSTR_ADDR_WIDTH,
72 -- instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
73 -- instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
79 fetch_st : fetch_stage
88 clk => sys_clk_pin, --: in std_logic;
89 reset => sys_res_n_pin, --: in std_logic;
92 jump_result => jump_result_pin, --: in instruction_addr_t;
93 prediction_result => prediction_result_pin, --: in instruction_addr_t;
94 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
95 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
98 instruction => instruction_pin, --: out instruction_word_t
102 decode_st : decode_stage
104 -- active reset value
106 -- active logic value
112 clk => sys_clk_pin, --: in std_logic;
113 reset => sys_res_n_pin, -- : in std_logic;
116 instruction => instruction_pin, --: in instruction_word_t;
117 prog_cnt => prog_cnt,
118 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
119 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
120 reg_we => reg_we_pin, --: in std_logic;
124 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
125 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
126 to_next_stage => to_next_stage_pin
129 exec_st : execute_stage
131 port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
132 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
134 writeback_st : writeback_stage
135 generic map('0', '1')
136 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
137 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
138 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, sseg0, sseg1, sseg2, sseg3);
143 nop_pin <= (alu_jump_bit_pin);-- xor brpr_pin);
145 -------------------------------------------------------------------------------
146 -- generate simulation clock
147 -------------------------------------------------------------------------------
157 cnt : process(sys_clk_pin, sys_res_n_pin)
161 if (sys_res_n_pin = '0') then
163 elsif (sys_clk_pin'event and sys_clk_pin = '1') then
164 cycle_cnt <= cycle_cnt + 1;
168 -------------------------------------------------------------------------------
170 -------------------------------------------------------------------------------
173 -- wait for n clock cycles
174 procedure icwait(cycles : natural) is
176 for i in 1 to cycles loop
177 wait until sys_clk_pin = '1' and sys_clk_pin'event;
182 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
185 sys_res_n_pin <= '0';
186 -- reg_w_addr_pin <= (others => '0');
187 -- reg_wr_data_pin <= (others => '0');
188 -- reg_we_pin <= '0';
192 sys_res_n_pin <= '1';
193 wait until sys_res_n_pin = '1';
198 ---------------------------------------------------------------------------
200 ---------------------------------------------------------------------------
202 report "Test finished"
210 -------------------------------------------------------------------------------
212 -------------------------------------------------------------------------------
213 configuration pipeline_conf_beh of pipeline_tb is
215 for fetch_st : fetch_stage use entity work.fetch_stage(behav);
217 for decode_st : decode_stage use entity work.decode_stage(behav);
219 for exec_st : execute_stage use entity work.execute_stage(behav);
221 for writeback_st : writeback_stage use entity work.writeback_stage(behav);
225 end pipeline_conf_beh;