2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
7 use work.extension_pkg.all;
8 -------------------------------------------------------------------------------
10 -------------------------------------------------------------------------------
16 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 architecture behavior of pipeline_tb is
21 constant cc : time := 30 ns; -- test clock period
23 signal sys_clk_pin : std_logic;
24 signal sys_res_n_pin : std_logic;
27 signal dummy : std_logic;
29 signal jump_result_pin : instruction_addr_t;
30 signal prediction_result_pin : instruction_addr_t;
31 signal branch_prediction_bit_pin : std_logic;
32 signal alu_jump_bit_pin : std_logic;
33 signal instruction_pin : instruction_word_t;
35 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
36 signal reg_wr_data_pin : gp_register_t;
37 signal reg_we_pin : std_logic;
38 signal to_next_stage_pin : dec_op;
40 signal result_pin : gp_register_t;--reg
41 signal result_addr_pin : gp_addr_t;--reg
42 signal addr_pin : word_t; --memaddr
43 signal data_pin : gp_register_t; --mem data --ureg
44 signal alu_jump_pin : std_logic;--reg
45 signal brpr_pin : std_logic; --reg
46 signal wr_en_pin : std_logic;--regop --reg
47 signal dmem_pin : std_logic;--memop
48 signal dmem_wr_en_pin : std_logic;
49 signal hword_pin : std_logic;
50 signal byte_s_pin : std_logic;
51 signal nop_pin : std_logic;
56 -- instruction_ram : r_w_ram
58 -- PHYS_INSTR_ADDR_WIDTH,
64 -- instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
65 -- instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
71 fetch_st : fetch_stage
80 clk => sys_clk_pin, --: in std_logic;
81 reset => sys_res_n_pin, --: in std_logic;
84 jump_result => jump_result_pin, --: in instruction_addr_t;
85 prediction_result => prediction_result_pin, --: in instruction_addr_t;
86 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
87 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
90 instruction => instruction_pin --: out instruction_word_t
93 decode_st : decode_stage
103 clk => sys_clk_pin, --: in std_logic;
104 reset => sys_res_n_pin, -- : in std_logic;
107 instruction => instruction_pin, --: in instruction_word_t;
108 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
109 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
110 reg_we => reg_we_pin, --: in std_logic;
114 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
115 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
116 to_next_stage => to_next_stage_pin
119 exec_st : execute_stage
121 port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin,
122 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
124 writeback_st : writeback_stage
125 generic map('0', '1')
126 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
127 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
128 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
133 nop_pin <= (alu_jump_bit_pin xor brpr_pin);
135 -------------------------------------------------------------------------------
136 -- generate simulation clock
137 -------------------------------------------------------------------------------
146 -------------------------------------------------------------------------------
148 -------------------------------------------------------------------------------
151 -- wait for n clock cycles
152 procedure icwait(cycles : natural) is
154 for i in 1 to cycles loop
155 wait until sys_clk_pin = '1' and sys_clk_pin'event;
160 -----------------------------------------------------------------------------
162 -----------------------------------------------------------------------------
163 sys_res_n_pin <= '0';
164 -- reg_w_addr_pin <= (others => '0');
165 -- reg_wr_data_pin <= (others => '0');
166 -- reg_we_pin <= '0';
170 sys_res_n_pin <= '1';
171 wait until sys_res_n_pin = '1';
176 ---------------------------------------------------------------------------
178 ---------------------------------------------------------------------------
180 report "Test finished"
188 -------------------------------------------------------------------------------
190 -------------------------------------------------------------------------------
191 configuration pipeline_conf_beh of pipeline_tb is
193 for fetch_st : fetch_stage use entity work.fetch_stage(behav);
195 for decode_st : decode_stage use entity work.decode_stage(behav);
197 for exec_st : execute_stage use entity work.execute_stage(behav);
199 for writeback_st : writeback_stage use entity work.writeback_stage(behav);
203 end pipeline_conf_beh;