3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
10 ADDR_WIDTH : integer range 1 to integer'high;
11 DATA_WIDTH : integer range 1 to integer'high
17 wr_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
20 data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
23 data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
25 end component r_w_ram;
27 component r_w_ram_be is
29 ADDR_WIDTH : integer range 1 to integer'high
34 waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
36 be : in std_logic_vector (3 downto 0);
40 wdata : in std_logic_vector(31 downto 0);
42 q : out std_logic_vector(31 downto 0)
44 end component r_w_ram_be;
46 component ram_xilinx is
47 generic ( ADDR_WIDTH : integer range 1 to integer'high);
48 port(clk : in std_logic;
49 addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
50 be : in std_logic_vector(3 downto 0);
51 we : in std_logic; -- dummy :/
52 wdata : in std_logic_vector(31 downto 0);
53 q : out std_logic_vector(31 downto 0)
55 end component ram_xilinx;
59 ADDR_WIDTH : integer range 1 to integer'high;
60 DATA_WIDTH : integer range 1 to integer'high
66 rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
68 data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
74 ADDR_WIDTH : integer range 1 to integer'high;
75 DATA_WIDTH : integer range 1 to integer'high
81 wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
84 data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
87 data_out1, data_out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
89 end component r2_w_ram;
93 ADDR_WIDTH : integer range 1 to integer'high;
94 DATA_WIDTH : integer range 1 to integer'high
100 rw_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
102 wr_en : in std_logic;
103 data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
106 rw_out, rd_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
108 end component rw_r_ram;