3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
10 ADDR_WIDTH : integer range 1 to integer'high;
11 DATA_WIDTH : integer range 1 to integer'high
17 wr_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
20 data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
23 data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
25 end component r_w_ram;
29 ADDR_WIDTH : integer range 1 to integer'high;
30 DATA_WIDTH : integer range 1 to integer'high
36 wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
39 data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
42 data_out1, data_out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
44 end component r2_w_ram;
48 ADDR_WIDTH : integer range 1 to integer'high;
49 DATA_WIDTH : integer range 1 to integer'high
55 rw_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
58 data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
61 rw_out, rd_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
63 end component rw_r_ram;