2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
6 use work.common_pkg.all;
9 architecture behav of fetch_stage is
11 signal instr_w_addr : instruction_addr_t;
12 signal instr_r_addr : instruction_addr_t;
13 signal instr_r_addr_nxt : instruction_addr_t;
14 signal instr_we : std_logic;
15 signal instr_wr_data : instruction_word_t;
16 signal instr_rd_data : instruction_word_t;
20 instruction_ram : r_w_ram
22 PHYS_INSTR_ADDR_WIDTH,
28 instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
29 instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
35 syn: process(clk, reset)
39 if (reset = RESET_VALUE) then
40 instr_r_addr <= (others => '0');
41 elsif rising_edge(clk) then
42 instr_r_addr <= instr_r_addr_nxt;
48 asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data)
52 instruction <= instr_rd_data;
53 instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
55 if (reset = RESET_VALUE) then
56 instr_r_addr_nxt <= (others => '0');
59 if (alu_jump_bit = LOGIC_ACT) then
60 instr_r_addr_nxt <= jump_result;
61 elsif (branch_prediction_bit = LOGIC_ACT) then
62 instr_r_addr_nxt <= prediction_result;