2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
6 use work.common_pkg.all;
9 architecture behav of fetch_stage is
11 signal instr_w_addr : instruction_addr_t;
12 signal instr_r_addr : instruction_addr_t;
13 signal instr_r_addr_nxt : instruction_addr_t;
14 signal instr_we : std_logic;
15 signal instr_wr_data : instruction_word_t;
16 signal instr_rd_data_rom, instr_rd_data : instruction_word_t;
17 signal rom_ram, rom_ram_nxt : std_logic;
21 instruction_ram : r_w_ram --rom
23 PHYS_INSTR_ADDR_WIDTH,
29 instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
30 instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
44 instr_r_addr_nxt(ROM_INSTR_ADDR_WIDTH-1 downto 0),
49 syn: process(clk, reset)
53 if (reset = RESET_VALUE) then
54 instr_r_addr <= (others => '0');
56 elsif rising_edge(clk) then
57 instr_r_addr <= instr_r_addr_nxt;
58 rom_ram <= rom_ram_nxt;
64 asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
68 rom_ram_nxt <= rom_ram;
72 instruction <= instr_rd_data_rom;
74 instruction <= instr_rd_data;
76 instruction <= x"F0000000";
78 instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
80 if (instr_r_addr(ROM_INSTR_ADDR_WIDTH) = '1' and rom_ram = ROM_USE) then
81 rom_ram_nxt <= RAM_USE;
82 instr_r_addr_nxt <= (others => '0');
85 if (reset = RESET_VALUE) then
86 instr_r_addr_nxt <= (others => '0');
89 if (alu_jump_bit = LOGIC_ACT) then
90 instr_r_addr_nxt <= jump_result;
91 instruction(31 downto 28) <= "1111";
92 elsif (branch_prediction_bit = LOGIC_ACT) then
93 instr_r_addr_nxt <= prediction_result;
98 instruction(31 downto 0) <= (others => '0');
99 instruction(31 downto 28) <= "1110";
100 instruction(27 downto 23) <= "10110";
101 instruction(PHYS_INSTR_ADDR_WIDTH + 7 - 1 downto 7) <= UART_INT_VECTOR;
102 instruction(6 downto 4) <= "001";
103 instruction(3 downto 2) <= "01";
104 instruction(1 downto 0) <= "10";
111 prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
112 prog_cnt(31 downto 11) <= (others => '0');