2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
9 use work.extension_pkg.all;
10 use work.extension_uart_pkg.all;
12 architecture behav of extension_uart is
14 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
15 signal new_wb_data, new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
16 signal bd_rate : baud_rate_l;
21 rs232_tx_inst : rs232_tx
35 w3_uart_send(byte_t'range),
45 syn : process (clk, reset)
47 if (reset = RESET_VALUE) then
48 w1_st_co <= (others=>'0');
49 w2_uart_config <= (others=>'0');
50 w3_uart_send <= (others=>'0');
51 w4_uart_receive <= (others=>'0');
54 elsif rising_edge(clk) then
55 w1_st_co <= w1_st_co_nxt;
56 w2_uart_config <= w2_uart_config_nxt;
57 w3_uart_send <= w3_uart_send_nxt;
58 w4_uart_receive <= w4_uart_receive_nxt;
59 new_tx_data <= new_tx_data_nxt;
64 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
66 gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int)
68 variable tmp_data : gp_register_t;
72 w1_st_co_nxt <= w1_st_co;
73 w2_uart_config_nxt <= w2_uart_config;
74 w3_uart_send_nxt <= w3_uart_send;
75 w4_uart_receive_nxt <= w4_uart_receive;
77 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
78 tmp_data := (others =>'0');
79 if ext_reg.byte_en(0) = '1' then
80 tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
82 if ext_reg.byte_en(1) = '1' then
83 tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
85 if ext_reg.byte_en(2) = '1' then
86 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
88 if ext_reg.byte_en(3) = '1' then
89 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
92 case ext_reg.addr(1 downto 0) is
94 w1_st_co_nxt <= tmp_data;
96 w2_uart_config_nxt <= tmp_data;
98 w1_st_co_nxt(16) <= '1'; -- busy flag set
99 w3_uart_send_nxt <= tmp_data;
101 w4_uart_receive_nxt <= tmp_data;
106 if tx_rdy = '1' and tx_rdy_int = '0' then
107 w1_st_co_nxt(16) <= '0'; -- busy flag reset
112 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
114 variable tmp_data : gp_register_t;
117 if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
118 case ext_reg.addr(1 downto 0) is
120 tmp_data := (others =>'0');
121 if ext_reg.byte_en(0) = '1' then
122 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
124 if ext_reg.byte_en(1) = '1' then
125 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
127 if ext_reg.byte_en(2) = '1' then
128 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
130 if ext_reg.byte_en(3) = '1' then
131 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
133 data_out <= tmp_data;
135 tmp_data := (others =>'0');
136 if ext_reg.byte_en(0) = '1' then
137 tmp_data(byte_t'range) := w2_uart_config(byte_t'range);
139 if ext_reg.byte_en(1) = '1' then
140 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_uart_config((2*byte_t'length-1) downto byte_t'length);
142 if ext_reg.byte_en(2) = '1' then
143 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_uart_config((3*byte_t'length-1) downto 2*byte_t'length);
145 if ext_reg.byte_en(3) = '1' then
146 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_uart_config((4*byte_t'length-1) downto 3*byte_t'length);
148 data_out <= tmp_data;
150 tmp_data := (others =>'0');
151 if ext_reg.byte_en(0) = '1' then
152 tmp_data(byte_t'range) := w3_uart_send(byte_t'range);
154 if ext_reg.byte_en(1) = '1' then
155 tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_uart_send((2*byte_t'length-1) downto byte_t'length);
157 if ext_reg.byte_en(2) = '1' then
158 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_uart_send((3*byte_t'length-1) downto 2*byte_t'length);
160 if ext_reg.byte_en(3) = '1' then
161 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_uart_send((4*byte_t'length-1) downto 3*byte_t'length);
163 data_out <= tmp_data;
165 tmp_data := (others =>'0');
166 if ext_reg.byte_en(0) = '1' then
167 tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
169 if ext_reg.byte_en(1) = '1' then
170 tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_uart_receive((2*byte_t'length-1) downto byte_t'length);
172 if ext_reg.byte_en(2) = '1' then
173 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_uart_receive((3*byte_t'length-1) downto 2*byte_t'length);
175 if ext_reg.byte_en(3) = '1' then
176 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_uart_receive((4*byte_t'length-1) downto 3*byte_t'length);
178 data_out <= tmp_data;
182 data_out <= (others=>'0');
187 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
189 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
191 dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
196 new_tx_data_nxt <= '0';
197 bd_rate <= w2_uart_config(15 downto 0);
199 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
200 case ext_reg.addr(1 downto 0) is
206 new_tx_data_nxt <= '1';
213 end process dataprocess;
217 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------