3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
8 use work.common_pkg.all;
11 architecture behav of decode_stage is
13 signal instr_spl : instruction_rec;
15 signal rtw_rec, rtw_rec_nxt : read_through_write_rec;
16 signal reg1_mem_data, reg2_mem_data, reg1_rd_data, reg2_rd_data : gp_register_t;
17 signal dec_op_inst, dec_op_inst_nxt : dec_op;
23 register_ram : r2_w_ram
32 instr_spl.reg_src1_addr,
33 instr_spl.reg_src2_addr,
41 decoder_inst : decoder
48 -- sync process for read through write registers
49 syn: process(clk, reset)
53 if (reset = RESET_VALUE) then
54 rtw_rec.rtw_reg <= (others => '0');
55 rtw_rec.rtw_reg1 <= '0';
56 rtw_rec.rtw_reg2 <= '0';
57 rtw_rec.immediate <= (others => '0');
58 rtw_rec.imm_set <= '0';
60 dec_op_inst.condition <= (others => '1');
61 dec_op_inst.op_detail <= (others => '0');
62 dec_op_inst.op_group <= ADDSUB_OP;
63 dec_op_inst.brpr <= '0'; --branch_prediction_bit;
64 dec_op_inst.src1 <= (others => '0');
65 dec_op_inst.src2 <= (others => '0');
66 dec_op_inst.saddr1 <= (others => '0');
67 dec_op_inst.saddr2 <= (others => '0');
68 dec_op_inst.daddr <= (others => '0');
69 dec_op_inst.displacement <= (others => '0');
70 dec_op_inst.prog_cnt <= (others => '0');
72 elsif rising_edge(clk) then
73 rtw_rec <= rtw_rec_nxt;
74 dec_op_inst <= dec_op_inst_nxt;
79 -- type dec_op is record
80 -- condition : condition_t;
81 -- op_group : op_info_t;
82 -- op_detail : op_opt_t;
85 -- src1 : gp_register_t;
86 -- src2 : gp_register_t;
88 -- saddr1 : gp_addr_t;
89 -- saddr2 : gp_addr_t;
95 -- output logic incl. bypassing reg-file
96 output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data, nop)
100 to_next_stage <= dec_op_inst;
101 to_next_stage.src1 <= reg1_rd_data;
102 to_next_stage.src2 <= reg2_rd_data;
105 to_next_stage.condition <= "1111";
111 -- fills output register
112 to_next: process(instr_spl, prog_cnt)
115 dec_op_inst_nxt.condition <= instr_spl.predicates;
116 dec_op_inst_nxt.op_detail <= instr_spl.op_detail;
117 dec_op_inst_nxt.brpr <= instr_spl.bp; --branch_prediction_bit;
118 dec_op_inst_nxt.src1 <= (others => '0');
119 dec_op_inst_nxt.src2 <= (others => '0');
120 dec_op_inst_nxt.saddr1 <= instr_spl.reg_src1_addr;
121 dec_op_inst_nxt.saddr2 <= instr_spl.reg_src2_addr;
122 dec_op_inst_nxt.daddr <= instr_spl.reg_dest_addr; --(others => '0');
123 dec_op_inst_nxt.op_group <= instr_spl.op_group;
124 dec_op_inst_nxt.displacement <= instr_spl.displacement;
125 dec_op_inst_nxt.prog_cnt <= prog_cnt;
129 -- async process: decides between memory and read-through-write buffer on output
130 output: process(rtw_rec, rtw_rec_nxt, reg1_mem_data, reg2_mem_data)
133 if ((rtw_rec.rtw_reg1) = '1') then
134 reg1_rd_data <= rtw_rec.rtw_reg;
136 reg1_rd_data <= reg1_mem_data;
139 if ((rtw_rec.rtw_reg2) = '1') then
140 reg2_rd_data <= rtw_rec.rtw_reg;
142 reg2_rd_data <= reg2_mem_data;
145 if (rtw_rec.imm_set = '1') then
146 reg2_rd_data <= rtw_rec.immediate;
152 -- async process: checks forward condition
153 forward: process(instr_spl, reg_w_addr, reg_wr_data, reg_we)
157 rtw_rec_nxt.rtw_reg <= reg_wr_data;
158 rtw_rec_nxt.rtw_reg1 <= '0';
159 rtw_rec_nxt.rtw_reg2 <= '0';
160 rtw_rec_nxt.immediate <= (others => '0');
161 rtw_rec_nxt.imm_set <= '0';
163 rtw_rec_nxt.reg1_addr <= instr_spl.reg_src1_addr;
164 rtw_rec_nxt.reg2_addr <= instr_spl.reg_src2_addr;
166 if (instr_spl.op_detail(IMM_OPT) = '1') then -- or instr_spl.op_group = LDST_OP
167 rtw_rec_nxt.immediate <= instr_spl.immediate;
168 rtw_rec_nxt.imm_set <= '1';
171 if (reg_w_addr = instr_spl.reg_src1_addr) then
172 rtw_rec_nxt.rtw_reg1 <= ('1' and reg_we);
175 if (reg_w_addr = instr_spl.reg_src2_addr) then
176 rtw_rec_nxt.rtw_reg2 <= ('1' and reg_we);
182 -- async process: calculates branch prediction
183 br_pred: process(instr_spl, prog_cnt, reset)
187 branch_prediction_res <= (others => '0');
188 branch_prediction_bit <= '0';
190 if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
191 if instr_spl.int = '0' then
192 branch_prediction_res <= std_logic_vector(unsigned(instr_spl.immediate) + unsigned(prog_cnt)); --both 32 bit
194 branch_prediction_res <= instr_spl.immediate;
196 branch_prediction_bit <= '1';
199 if reset = RESET_VALUE then
200 branch_prediction_bit <= '0';