2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
7 use work.extension_pkg.all;
13 sys_res : in std_logic;
14 soft_res : in std_logic;
15 sys_clk : in std_logic;
16 -- result : out gp_register_t;
17 -- reg_wr_data : out gp_register_t
19 bus_tx : out std_logic;
20 bus_rx : in std_logic;
24 sseg0 : out std_logic_vector(0 to 6);
25 sseg1 : out std_logic_vector(0 to 6);
26 sseg2 : out std_logic_vector(0 to 6);
27 sseg3 : out std_logic_vector(0 to 6)
32 architecture behav of core_top is
34 constant SYNC_STAGES : integer := 2;
35 constant RESET_VALUE : std_logic := '0';
37 signal jump_result : instruction_addr_t;
38 signal jump_result_pin : instruction_addr_t;
39 signal prediction_result_pin : instruction_addr_t;
40 signal branch_prediction_bit_pin : std_logic;
41 signal alu_jump_bit_pin : std_logic;
42 signal instruction_pin : instruction_word_t;
43 signal prog_cnt_pin : instruction_addr_t;
45 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
46 signal reg_wr_data_pin : gp_register_t;
47 signal reg_we_pin : std_logic;
48 signal to_next_stage : dec_op;
50 -- signal reg1_rd_data_pin : gp_register_t;
51 -- signal reg2_rd_data_pin : gp_register_t;
53 signal result_pin : gp_register_t;--reg
54 signal result_addr_pin : gp_addr_t;--reg
55 signal addr_pin : word_t; --memaddr
56 signal data_pin : gp_register_t; --mem data --ureg
57 signal alu_jump_pin : std_logic;--reg
58 signal brpr_pin : std_logic; --reg
59 signal wr_en_pin : std_logic;--regop --reg
60 signal dmem_pin : std_logic;--memop
61 signal dmem_wr_en_pin : std_logic;
62 signal hword_pin : std_logic;
63 signal byte_s_pin : std_logic;
65 signal gpm_in_pin : extmod_rec;
66 signal gpm_out_pin : gp_register_t;
67 signal nop_pin : std_logic;
69 signal sync, sync2 : std_logic_vector(1 to SYNC_STAGES);
70 signal sys_res_n, soft_res_n : std_logic;
71 signal xilinxfail : std_logic;
73 signal int_req : interrupt_t;
75 signal new_im_data : std_logic;
76 signal im_addr, im_data : gp_register_t;
78 signal vers, vers_nxt : exec2wb_rec;
81 fetch_st : fetch_stage
90 clk => sys_clk, --: in std_logic;
91 reset => sys_res_n, --: in std_logic;
92 s_reset => soft_res_n,
94 jump_result => jump_result_pin, --: in instruction_addr_t;
95 prediction_result => prediction_result_pin, --: in instruction_addr_t;
96 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
97 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
99 -- instruction memory program port :D
100 new_im_data_in => new_im_data,
104 instruction => instruction_pin, --: out instruction_word_t
105 prog_cnt => prog_cnt_pin,
109 decode_st : decode_stage
111 -- active reset value
113 -- active logic value
119 clk => sys_clk, --: in std_logic;
120 reset => xilinxfail, -- : in std_logic;
123 instruction => instruction_pin, --: in instruction_word_t;
124 prog_cnt => prog_cnt_pin,
125 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
126 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
127 reg_we => reg_we_pin, --: in std_logic;
131 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
132 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
133 to_next_stage => to_next_stage
136 exec_st : execute_stage
138 port map(sys_clk, xilinxfail,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
139 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
142 vers_nxt.result <= result_pin;
143 vers_nxt.result_addr <= result_addr_pin;
144 vers_nxt.address <= addr_pin;
145 vers_nxt.ram_data <= data_pin;
146 vers_nxt.alu_jmp <= alu_jump_pin;
147 vers_nxt.br_pred <= brpr_pin;
148 vers_nxt.write_en <= wr_en_pin;
149 vers_nxt.dmem_en <= dmem_pin;
150 vers_nxt.dmem_write_en <= dmem_wr_en_pin;
151 vers_nxt.hword <= hword_pin;
152 vers_nxt.byte_s <= byte_s_pin;
154 -- writeback_st : writeback_stage
155 -- generic map('0', '1')
156 -- port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
157 -- wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
158 -- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
161 writeback_st : writeback_stage
162 generic map('0', '1', "s3e", 434)
163 port map(sys_clk, xilinxfail, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
164 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
165 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
166 -- instruction memory program port :D
167 new_im_data, im_addr, im_data,
168 sseg0, sseg1, sseg2, sseg3, int_req);
171 syn: process(sys_clk, sys_res)
175 if sys_res = '1' then
177 -- vers.result <= (others => '0');
178 -- vers.result_addr <= (others => '0');
179 -- vers.address <= (others => '0');
180 -- vers.ram_data <= (others => '0');
181 -- vers.alu_jmp <= '0';
182 -- vers.br_pred <= '0';
183 -- vers.write_en <= '0';
184 -- vers.dmem_en <= '0';
185 -- vers.dmem_write_en <= '0';
186 -- vers.hword <= '0';
187 -- vers.byte_s <= '0';
189 sync <= (others => '0');
190 sync2 <= (others => '0');
192 elsif rising_edge(sys_clk) then
195 sync(1) <= not sys_res;
196 for i in 2 to SYNC_STAGES loop
197 sync(i) <= sync(i - 1);
199 sync2(1) <= not soft_res;
200 for i in 2 to SYNC_STAGES loop
201 sync2(i) <= sync2(i - 1);
207 sys_res_n <= sync(SYNC_STAGES);
208 soft_res_n <= sync2(SYNC_STAGES);
209 xilinxfail <= sys_res_n and soft_res_n;
211 --init : process(all)
214 -- jump_result_pin <= (others => '0');
215 -- alu_jump_bit_pin <= '0';
216 -- reg_w_addr_pin <= (others => '0');
217 -- reg_wr_data_pin <= (others => '0');
218 -- reg_we_pin <= '0';
222 -- result <= result_pin;
223 nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
225 jump_result <= prog_cnt_pin; --jump_result_pin;
228 -- reg_wr_data <= reg_wr_data_pin;