2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
12 sys_clk : in std_logic;
13 sys_res : in std_logic;
14 result : out gp_register_t;
15 jump_result : out instruction_addr_t;
16 reg_wr_data : out gp_register_t
22 architecture behav of core_top is
24 signal jump_result_pin : instruction_addr_t;
25 signal prediction_result_pin : instruction_addr_t;
26 signal branch_prediction_bit_pin : std_logic;
27 signal alu_jump_bit_pin : std_logic;
28 signal instruction_pin : instruction_word_t;
30 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
31 signal reg_wr_data_pin : gp_register_t;
32 signal reg_we_pin : std_logic;
33 signal to_next_stage : dec_op;
35 -- signal reg1_rd_data_pin : gp_register_t;
36 -- signal reg2_rd_data_pin : gp_register_t;
38 signal result_pin : gp_register_t;--reg
39 signal result_addr_pin : gp_addr_t;--reg
40 signal addr_pin : word_t; --memaddr
41 signal data_pin : gp_register_t; --mem data --ureg
42 signal alu_jump_pin : std_logic;--reg
43 signal brpr_pin : std_logic; --reg
44 signal wr_en_pin : std_logic;--regop --reg
45 signal dmem_pin : std_logic;--memop
46 signal dmem_wr_en_pin : std_logic;
47 signal hword_pin : std_logic;
48 signal byte_s_pin : std_logic;
49 signal nop_pin : std_logic;
51 signal ext_gpmp : extmod_rec;
52 signal pointer : pointer_count;
53 signal dec_in,p_en : std_logic;
54 signal data_out : gp_register_t;
55 signal pointer_val : gp_register_t;
60 fetch_st : fetch_stage
69 clk => sys_clk, --: in std_logic;
70 reset => sys_res, --: in std_logic;
73 jump_result => jump_result_pin, --: in instruction_addr_t;
74 prediction_result => prediction_result_pin, --: in instruction_addr_t;
75 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
76 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
79 instruction => instruction_pin --: out instruction_word_t
82 decode_st : decode_stage
92 clk => sys_clk, --: in std_logic;
93 reset => sys_res, -- : in std_logic;
96 instruction => instruction_pin, --: in instruction_word_t;
97 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
98 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
99 reg_we => reg_we_pin, --: in std_logic;
103 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
104 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
105 to_next_stage => to_next_stage
108 exec_st : execute_stage
110 port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin,
111 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
113 writeback_st : writeback_stage
114 generic map('0', '1')
115 port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
116 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
117 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
120 gpmp_inst : extension
135 --init : process(all)
138 -- jump_result_pin <= (others => '0');
139 -- alu_jump_bit_pin <= '0';
140 -- reg_w_addr_pin <= (others => '0');
141 -- reg_wr_data_pin <= (others => '0');
142 -- reg_we_pin <= '0';
146 result <= result_pin;
147 nop_pin <= (alu_jump_bit_pin xor brpr_pin);
149 jump_result <= jump_result_pin;
151 reg_wr_data <= reg_wr_data_pin;