2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
7 use work.extension_pkg.all;
13 sys_res : in std_logic;
14 sys_clk : in std_logic;
15 -- result : out gp_register_t;
16 -- reg_wr_data : out gp_register_t
18 bus_tx : out std_logic;
19 bus_rx : in std_logic;
21 sseg0 : out std_logic_vector(0 to 6);
22 sseg1 : out std_logic_vector(0 to 6);
23 sseg2 : out std_logic_vector(0 to 6);
24 sseg3 : out std_logic_vector(0 to 6)
29 architecture behav of core_top is
31 signal jump_result : instruction_addr_t;
32 signal jump_result_pin : instruction_addr_t;
33 signal prediction_result_pin : instruction_addr_t;
34 signal branch_prediction_bit_pin : std_logic;
35 signal alu_jump_bit_pin : std_logic;
36 signal instruction_pin : instruction_word_t;
37 signal prog_cnt_pin : instruction_addr_t;
39 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
40 signal reg_wr_data_pin : gp_register_t;
41 signal reg_we_pin : std_logic;
42 signal to_next_stage : dec_op;
44 -- signal reg1_rd_data_pin : gp_register_t;
45 -- signal reg2_rd_data_pin : gp_register_t;
47 signal result_pin : gp_register_t;--reg
48 signal result_addr_pin : gp_addr_t;--reg
49 signal addr_pin : word_t; --memaddr
50 signal data_pin : gp_register_t; --mem data --ureg
51 signal alu_jump_pin : std_logic;--reg
52 signal brpr_pin : std_logic; --reg
53 signal wr_en_pin : std_logic;--regop --reg
54 signal dmem_pin : std_logic;--memop
55 signal dmem_wr_en_pin : std_logic;
56 signal hword_pin : std_logic;
57 signal byte_s_pin : std_logic;
59 signal gpm_in_pin : extmod_rec;
60 signal gpm_out_pin : gp_register_t;
61 signal nop_pin : std_logic;
63 signal vers, vers_nxt : exec2wb_rec;
67 fetch_st : fetch_stage
76 clk => sys_clk, --: in std_logic;
77 reset => sys_res, --: in std_logic;
80 jump_result => jump_result_pin, --: in instruction_addr_t;
81 prediction_result => prediction_result_pin, --: in instruction_addr_t;
82 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
83 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
86 instruction => instruction_pin, --: out instruction_word_t
87 prog_cnt => prog_cnt_pin
90 decode_st : decode_stage
100 clk => sys_clk, --: in std_logic;
101 reset => sys_res, -- : in std_logic;
104 instruction => instruction_pin, --: in instruction_word_t;
105 prog_cnt => prog_cnt_pin,
106 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
107 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
108 reg_we => reg_we_pin, --: in std_logic;
112 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
113 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
114 to_next_stage => to_next_stage
117 exec_st : execute_stage
119 port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
120 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
123 vers_nxt.result <= result_pin;
124 vers_nxt.result_addr <= result_addr_pin;
125 vers_nxt.address <= addr_pin;
126 vers_nxt.ram_data <= data_pin;
127 vers_nxt.alu_jmp <= alu_jump_pin;
128 vers_nxt.br_pred <= brpr_pin;
129 vers_nxt.write_en <= wr_en_pin;
130 vers_nxt.dmem_en <= dmem_pin;
131 vers_nxt.dmem_write_en <= dmem_wr_en_pin;
132 vers_nxt.hword <= hword_pin;
133 vers_nxt.byte_s <= byte_s_pin;
135 -- writeback_st : writeback_stage
136 -- generic map('0', '1')
137 -- port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
138 -- wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
139 -- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
142 writeback_st : writeback_stage
143 generic map('0', '1')
144 port map(sys_clk, sys_res, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
145 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
146 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, sseg0, sseg1, sseg2, sseg3);
149 syn: process(sys_clk, sys_res)
153 if sys_res = '0' then
154 vers.result <= (others => '0');
155 vers.result_addr <= (others => '0');
156 vers.address <= (others => '0');
157 vers.ram_data <= (others => '0');
160 vers.write_en <= '0';
162 vers.dmem_write_en <= '0';
165 elsif rising_edge(sys_clk) then
172 --init : process(all)
175 -- jump_result_pin <= (others => '0');
176 -- alu_jump_bit_pin <= '0';
177 -- reg_w_addr_pin <= (others => '0');
178 -- reg_wr_data_pin <= (others => '0');
179 -- reg_we_pin <= '0';
183 -- result <= result_pin;
184 nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
186 jump_result <= prog_cnt_pin; --jump_result_pin;
189 -- reg_wr_data <= reg_wr_data_pin;