1 # Copyright (C) 1991-2010 Altera Corporation
2 # Your use of Altera Corporation's design tools, logic functions
3 # and other software and tools, and its AMPP partner logic
4 # functions, and any output files from any of the foregoing
5 # (including device programming or simulation files), and any
6 # associated documentation or information are expressly subject
7 # to the terms and conditions of the Altera Program License
8 # Subscription Agreement, Altera MegaCore Function License
9 # Agreement, or other applicable license agreement, including,
10 # without limitation, that your use is for the sole purpose of
11 # programming logic devices manufactured by Altera and sold by
12 # Altera or its authorized distributors. Please refer to the
13 # applicable agreement for further details.
15 # Quartus II: Generate Tcl File for Project
16 # File: de1_cyclone_fmax.tcl
17 # Generated on: Mon Dec 20 19:47:21 2010
19 # Load Quartus II Tcl Project package
20 package require ::quartus::project
22 set need_to_close_project 0
23 set make_assignments 1
25 # Check that the right project is open
26 if {[is_project_open]} {
27 if {[string compare $quartus(project) "de1_cyclone"]} {
28 puts "Project de1_cyclone is not open"
29 set make_assignments 0
32 # Only open if not already open
33 if {[project_exists de1_cyclone]} {
34 project_open -revision de1_cyclone de1_cyclone
36 project_new -revision de1_cyclone de1_cyclone
38 set need_to_close_project 1
42 if {$make_assignments} {
43 set_global_assignment -name FAMILY "Cyclone II"
44 set_global_assignment -name DEVICE EP2C20F484C7
45 set_global_assignment -name TOP_LEVEL_ENTITY core_top
46 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
47 set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:41:06 DECEMBER 20, 2010"
48 set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
49 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
50 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
51 set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
52 set_global_assignment -name MISC_FILE de1_cyclone.dpf
53 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
54 set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
55 set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
56 set_global_assignment -name VHDL_FILE ../src/core_top.vhd
57 set_global_assignment -name VHDL_FILE ../src/mem_pkg.vhd
58 set_global_assignment -name VHDL_FILE ../src/r_w_ram.vhd
59 set_global_assignment -name VHDL_FILE ../src/r_w_ram_b.vhd
60 set_global_assignment -name VHDL_FILE ../src/r_w_ram_be.vhd
61 set_global_assignment -name VHDL_FILE ../src/r_w_ram_be_b.vhd
62 set_global_assignment -name VHDL_FILE ../src/rom.vhd
63 set_global_assignment -name VHDL_FILE ../src/rom_b.vhd
64 set_global_assignment -name VHDL_FILE ../src/r2_w_ram.vhd
65 set_global_assignment -name VHDL_FILE ../src/r2_w_ram_b.vhd
66 set_global_assignment -name VHDL_FILE ../src/common_pkg.vhd
67 set_global_assignment -name VHDL_FILE ../src/core_pkg.vhd
68 set_global_assignment -name VHDL_FILE ../src/fetch_stage.vhd
69 set_global_assignment -name VHDL_FILE ../src/fetch_stage_b.vhd
70 set_global_assignment -name VHDL_FILE ../src/decoder.vhd
71 set_global_assignment -name VHDL_FILE ../src/decoder_b.vhd
72 set_global_assignment -name VHDL_FILE ../src/decode_stage.vhd
73 set_global_assignment -name VHDL_FILE ../src/decode_stage_b.vhd
74 set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
75 set_global_assignment -name VHDL_FILE ../src/extension_uart_pkg.vhd
76 set_global_assignment -name VHDL_FILE ../src/extension_uart.vhd
77 set_global_assignment -name VHDL_FILE ../src/extension_uart_b.vhd
78 set_global_assignment -name VHDL_FILE ../src/rs232_tx.vhd
79 set_global_assignment -name VHDL_FILE ../src/rs232_tx_arc.vhd
80 set_global_assignment -name VHDL_FILE ../src/rs232_rx.vhd
81 set_global_assignment -name VHDL_FILE ../src/rs232_rx_arc.vhd
82 set_global_assignment -name VHDL_FILE ../src/extension_7seg_pkg.vhd
83 set_global_assignment -name VHDL_FILE ../src/extension_7seg.vhd
84 set_global_assignment -name VHDL_FILE ../src/extension_7seg_b.vhd
85 set_global_assignment -name VHDL_FILE ../src/alu_pkg.vhd
86 set_global_assignment -name VHDL_FILE ../src/extension.vhd
87 set_global_assignment -name VHDL_FILE ../src/extension_b.vhd
88 set_global_assignment -name VHDL_FILE ../src/exec_op.vhd
89 set_global_assignment -name VHDL_FILE ../src/exec_op/add_op_b.vhd
90 set_global_assignment -name VHDL_FILE ../src/exec_op/and_op_b.vhd
91 set_global_assignment -name VHDL_FILE ../src/exec_op/or_op_b.vhd
92 set_global_assignment -name VHDL_FILE ../src/exec_op/xor_op_b.vhd
93 set_global_assignment -name VHDL_FILE ../src/exec_op/shift_op_b.vhd
94 set_global_assignment -name VHDL_FILE ../src/alu.vhd
95 set_global_assignment -name VHDL_FILE ../src/alu_b.vhd
96 set_global_assignment -name VHDL_FILE ../src/execute_stage.vhd
97 set_global_assignment -name VHDL_FILE ../src/execute_stage_b.vhd
98 set_global_assignment -name VHDL_FILE ../src/writeback_stage.vhd
99 set_global_assignment -name VHDL_FILE ../src/writeback_stage_b.vhd
100 set_global_assignment -name FMAX_REQUIREMENT "80 MHz" -section_id sys_clk
101 set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
102 set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
103 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
104 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
105 set_global_assignment -name SMART_RECOMPILE ON
106 set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
107 set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
108 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
109 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
110 set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
111 set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
112 set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
113 set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
114 set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
115 set_global_assignment -name MUX_RESTRUCTURE OFF
116 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
117 set_location_assignment PIN_L1 -to sys_clk
118 set_location_assignment PIN_R22 -to sys_res
119 set_location_assignment PIN_G12 -to bus_tx
120 set_location_assignment PIN_F14 -to bus_rx
121 set_location_assignment PIN_J2 -to sseg0[0]
122 set_location_assignment PIN_J1 -to sseg0[1]
123 set_location_assignment PIN_H2 -to sseg0[2]
124 set_location_assignment PIN_H1 -to sseg0[3]
125 set_location_assignment PIN_F2 -to sseg0[4]
126 set_location_assignment PIN_F1 -to sseg0[5]
127 set_location_assignment PIN_E2 -to sseg0[6]
128 set_location_assignment PIN_E1 -to sseg1[0]
129 set_location_assignment PIN_H6 -to sseg1[1]
130 set_location_assignment PIN_H5 -to sseg1[2]
131 set_location_assignment PIN_H4 -to sseg1[3]
132 set_location_assignment PIN_G3 -to sseg1[4]
133 set_location_assignment PIN_D2 -to sseg1[5]
134 set_location_assignment PIN_D1 -to sseg1[6]
135 set_location_assignment PIN_G5 -to sseg2[0]
136 set_location_assignment PIN_G6 -to sseg2[1]
137 set_location_assignment PIN_C2 -to sseg2[2]
138 set_location_assignment PIN_C1 -to sseg2[3]
139 set_location_assignment PIN_E3 -to sseg2[4]
140 set_location_assignment PIN_E4 -to sseg2[5]
141 set_location_assignment PIN_D3 -to sseg2[6]
142 set_location_assignment PIN_F4 -to sseg3[0]
143 set_location_assignment PIN_D5 -to sseg3[1]
144 set_location_assignment PIN_D6 -to sseg3[2]
145 set_location_assignment PIN_J4 -to sseg3[3]
146 set_location_assignment PIN_L8 -to sseg3[4]
147 set_location_assignment PIN_F3 -to sseg3[5]
148 set_location_assignment PIN_D4 -to sseg3[6]
149 set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
150 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
156 if {$need_to_close_project} {