cpu/create_project.tcl

   1 package require ::quartus::project\r
   2 \r
   3 set need_to_close_project 0\r
   4 set make_assignments 1\r
   5 \r
   6 # Check that the right project is open\r
   7 if {[is_project_open]} {\r
   8         if {[string compare $quartus(project) "de1_cyclone"]} {\r
   9                 puts "Project de1_cyclone is not open"\r
  10                 set make_assignments 0\r
  11         }\r
  12 } else {\r
  13         # Only open if not already open\r
  14         if {[project_exists de1_cyclone]} {\r
  15                 project_open -revision de1_cyclone de1_cyclone\r
  16         } else {\r
  17                 project_new -revision de1_cyclone de1_cyclone\r
  18         }\r
  19         set need_to_close_project 1\r
  20 }\r
  21 \r
  22 # Make assignments\r
  23 if {$make_assignments} {\r
  24         set_global_assignment -name FAMILY "Cyclone II"\r
  25         set_global_assignment -name DEVICE EP2C20F484C7\r
  26         set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"\r
  27         set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation\r
  28         set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga\r
  29         set_global_assignment -name MISC_FILE "de1_cyclone.dpf"\r
  30         set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"\r
  31         set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"\r
  32         set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"\r
  33 \r
  34         set_global_assignment -name TOP_LEVEL_ENTITY de1_test_top\r
  35         set_global_assignment -name VHDL_FILE ../../math_pkg.vhd\r
  36         set_global_assignment -name VHDL_FILE ../../de1_test_top.vhd\r
  37         set_global_assignment -name VHDL_FILE ../../DE1_7SEG/src/DE1_7SEG_PKG.vhd\r
  38         set_global_assignment -name VHDL_FILE ../../DE1_7SEG/src/DE1_7SEG_ENT.vhd\r
  39         set_global_assignment -name VHDL_FILE ../../DE1_7SEG/src/DE1_7SEG_ARC.vhd\r
  40         set_global_assignment -name VHDL_FILE ../../UART/rs232_pak.vhd\r
  41         set_global_assignment -name VHDL_FILE ../../UART/rs232_ent.vhd\r
  42         set_global_assignment -name VHDL_FILE ../../UART/rs232_arc.vhd\r
  43         set_global_assignment -name VHDL_FILE ../../PS2/ps2_pak.vhd\r
  44         set_global_assignment -name VHDL_FILE ../../PS2/ps2_ENT.vhd\r
  45         set_global_assignment -name VHDL_FILE ../../PS2/ps2_ARC.vhd\r
  46         set_global_assignment -name VHDL_FILE ../../ram/ram_pkg.vhd\r
  47         set_global_assignment -name VHDL_FILE ../../ram/dp_ram_ent.vhd\r
  48         set_global_assignment -name VHDL_FILE ../../ram/dp_ram_arc.vhd\r
  49         \r
  50         set_location_assignment PIN_L1 -to sys_clk\r
  51         set_location_assignment PIN_R22 -to sys_res\r
  52 \r
  53         set_location_assignment PIN_J2 -to o_digit0[0]\r
  54         set_location_assignment PIN_J1 -to o_digit0[1]\r
  55         set_location_assignment PIN_H2 -to o_digit0[2]\r
  56         set_location_assignment PIN_H1 -to o_digit0[3]\r
  57         set_location_assignment PIN_F2 -to o_digit0[4]\r
  58         set_location_assignment PIN_F1 -to o_digit0[5]\r
  59         set_location_assignment PIN_E2 -to o_digit0[6]\r
  60 \r
  61         set_location_assignment PIN_E1 -to o_digit1[0]\r
  62         set_location_assignment PIN_H6 -to o_digit1[1]\r
  63         set_location_assignment PIN_H5 -to o_digit1[2]\r
  64         set_location_assignment PIN_H4 -to o_digit1[3]\r
  65         set_location_assignment PIN_G3 -to o_digit1[4]\r
  66         set_location_assignment PIN_D2 -to o_digit1[5]\r
  67         set_location_assignment PIN_D1 -to o_digit1[6]\r
  68 \r
  69         set_location_assignment PIN_G5 -to o_digit2[0]\r
  70         set_location_assignment PIN_G6 -to o_digit2[1]\r
  71         set_location_assignment PIN_C2 -to o_digit2[2]\r
  72         set_location_assignment PIN_C1 -to o_digit2[3]\r
  73         set_location_assignment PIN_E3 -to o_digit2[4]\r
  74         set_location_assignment PIN_E4 -to o_digit2[5]\r
  75         set_location_assignment PIN_D3 -to o_digit2[6]\r
  76 \r
  77         set_location_assignment PIN_F4 -to o_digit3[0]\r
  78         set_location_assignment PIN_D5 -to o_digit3[1]\r
  79         set_location_assignment PIN_D6 -to o_digit3[2]\r
  80         set_location_assignment PIN_J4 -to o_digit3[3]\r
  81         set_location_assignment PIN_L8 -to o_digit3[4]\r
  82         set_location_assignment PIN_F3 -to o_digit3[5]\r
  83         set_location_assignment PIN_D4 -to o_digit3[6]\r
  84 \r
  85         set_location_assignment PIN_F14 -to rxd\r
  86         set_location_assignment PIN_G12 -to txd\r
  87         \r
  88         set_location_assignment PIN_H15 -to ps2_clk\r
  89         set_location_assignment PIN_J14 -to ps2_data\r
  90 \r
  91         set_global_assignment -name FMAX_REQUIREMENT "50.00 MHz" -section_id sys_clk\r
  92         set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk\r
  93 \r
  94         set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"\r
  95         set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"\r
  96         set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\r
  97         set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\r
  98         set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top\r
  99 \r
 100         # Commit assignments\r
 101         export_assignments\r
 102 \r
 103         # Close project\r
 104         if {$need_to_close_project} {\r
 105                 project_close\r
 106         }\r
 107 }\r