1 package require ::quartus::project
3 set need_to_close_project 0
6 # Check that the right project is open
7 if {[is_project_open]} {
8 if {[string compare $quartus(project) "de1_cyclone"]} {
9 puts "Project de1_cyclone is not open"
10 set make_assignments 0
13 # Only open if not already open
14 if {[project_exists de1_cyclone]} {
15 project_open -revision de1_cyclone de1_cyclone
17 project_new -revision de1_cyclone de1_cyclone
19 set need_to_close_project 1
23 if {$make_assignments} {
24 set_global_assignment -name FAMILY "Cyclone II"
25 set_global_assignment -name DEVICE EP2C20F484C7
26 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
27 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
28 set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
29 set_global_assignment -name MISC_FILE "de1_cyclone.dpf"
30 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
31 set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
32 set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
34 set_global_assignment -name TOP_LEVEL_ENTITY core_top
35 set_global_assignment -name VHDL_FILE ../src/core_top.vhd
36 set_global_assignment -name VHDL_FILE ../src/mem_pkg.vhd
37 set_global_assignment -name VHDL_FILE ../src/r_w_ram.vhd
38 set_global_assignment -name VHDL_FILE ../src/r_w_ram_b.vhd
39 set_global_assignment -name VHDL_FILE ../src/r2_w_ram.vhd
40 set_global_assignment -name VHDL_FILE ../src/r2_w_ram_b.vhd
41 set_global_assignment -name VHDL_FILE ../src/common_pkg.vhd
42 set_global_assignment -name VHDL_FILE ../src/core_pkg.vhd
43 set_global_assignment -name VHDL_FILE ../src/fetch_stage.vhd
44 set_global_assignment -name VHDL_FILE ../src/fetch_stage_b.vhd
45 set_global_assignment -name VHDL_FILE ../src/decoder.vhd
46 set_global_assignment -name VHDL_FILE ../src/decoder_b.vhd
47 set_global_assignment -name VHDL_FILE ../src/decode_stage.vhd
48 set_global_assignment -name VHDL_FILE ../src/decode_stage_b.vhd
50 set_global_assignment -name VHDL_FILE ../src/alu_pkg.vhd
52 set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
53 set_global_assignment -name VHDL_FILE ../src/gpm_pkg.vhd
55 set_global_assignment -name VHDL_FILE ../src/exec_op.vhd
56 set_global_assignment -name VHDL_FILE ../src/exec_op/add_op_b.vhd
57 set_global_assignment -name VHDL_FILE ../src/exec_op/and_op_b.vhd
58 set_global_assignment -name VHDL_FILE ../src/exec_op/or_op_b.vhd
59 set_global_assignment -name VHDL_FILE ../src/exec_op/xor_op_b.vhd
60 set_global_assignment -name VHDL_FILE ../src/exec_op/shift_op_b.vhd
62 set_global_assignment -name VHDL_FILE ../src/alu.vhd
63 set_global_assignment -name VHDL_FILE ../src/alu_b.vhd
65 set_global_assignment -name VHDL_FILE ../src/gpm.vhd
66 set_global_assignment -name VHDL_FILE ../src/gpm_b.vhd
68 set_global_assignment -name VHDL_FILE ../src/execute_stage.vhd
69 set_global_assignment -name VHDL_FILE ../src/execute_stage_b.vhd
72 set_global_assignment -name VHDL_FILE ../src/writeback_stage.vhd
73 set_global_assignment -name VHDL_FILE ../src/writeback_stage_b.vhd
76 set_location_assignment PIN_L1 -to sys_clk
77 set_location_assignment PIN_R22 -to sys_res
79 set_global_assignment -name FMAX_REQUIREMENT "80.00 MHz" -section_id sys_clk
80 set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
82 set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
83 set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
84 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
85 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
86 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
92 if {$need_to_close_project} {