1 #Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
2 #install: /opt/synplify/fpga_c200906
8 #Wed Oct 21 17:21:16 2009
11 #Wed Oct 21 17:21:16 2009
13 Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
14 Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved
16 @N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
17 @N:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Top entity is set to vga.
18 VHDL syntax check successful!
19 @N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Synthesizing work.vga.behav
20 @N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
21 @N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
22 @N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd":37:7:37:17|Synthesizing work.vga_control.behav
23 @E: CD395 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd":50:73:50:95|Constant width 21 does not match context width 25
24 @N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd":37:7:37:16|Synthesizing work.vga_driver.behav
25 @N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
26 @N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
27 @N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd":36:7:36:18|Synthesizing work.board_driver.behav
28 1 errors during synthesis
30 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
31 # Wed Oct 21 17:21:16 2009
33 ###########################################################]