1 -- megafunction wizard: %ALTPLL%
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2 -- GENERATION: STANDARD
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6 -- ============================================================
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7 -- File Name: vpll.vhd
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8 -- Megafunction Name(s):
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10 -- ============================================================
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11 -- ************************************************************
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12 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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14 -- 4.1 Build 181 06/29/2004 SJ Full Version
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15 -- ************************************************************
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18 --Copyright (C) 1991-2004 Altera Corporation
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19 --Any megafunction design, and related netlist (encrypted or decrypted),
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20 --support information, device programming or simulation file, and any other
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21 --associated documentation or information provided by Altera or a partner
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22 --under Altera's Megafunction Partnership Program may be used only
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23 --to program PLD devices (but not masked PLD devices) from Altera. Any
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24 --other use of such megafunction design, netlist, support information,
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25 --device programming or simulation file, or any other related documentation
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26 --or information is prohibited for any other purpose, including, but not
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27 --limited to modification, reverse engineering, de-compiling, or use with
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28 --any other silicon devices, unless such use is explicitly licensed under
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29 --a separate agreement with Altera or a megafunction partner. Title to the
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30 --intellectual property, including patents, copyrights, trademarks, trade
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31 --secrets, or maskworks, embodied in any such megafunction design, netlist,
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32 --support information, device programming or simulation file, or any other
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33 --related documentation or information provided by Altera or a megafunction
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34 --partner, remains with Altera, the megafunction partner, or their respective
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35 --licensors. No other licenses, including any licenses needed under any third
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36 --party's intellectual property, are provided herein.
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40 USE ieee.std_logic_1164.all;
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43 USE altera_mf.altera_mf_components.all;
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48 inclk0 : IN STD_LOGIC := '0';
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49 -- pllena : IN STD_LOGIC := '1';
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50 -- areset : IN STD_LOGIC := '0';
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52 -- locked : OUT STD_LOGIC
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57 ARCHITECTURE SYN OF vpll IS
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59 SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
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60 SIGNAL sub_wire1 : STD_LOGIC ;
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61 SIGNAL sub_wire2 : STD_LOGIC ;
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62 SIGNAL sub_wire3_bv : BIT_VECTOR (0 DOWNTO 0);
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63 SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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64 SIGNAL sub_wire4 : STD_LOGIC_VECTOR (5 DOWNTO 0);
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65 SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
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66 SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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67 SIGNAL sub_wire6 : STD_LOGIC ;
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68 SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
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69 SIGNAL sub_wire8 : STD_LOGIC_VECTOR (3 DOWNTO 0);
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71 signal pllena_int : std_logic;
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72 signal areset_int : std_logic;
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73 signal locked : std_logic;
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77 bandwidth_type : STRING;
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78 clk0_duty_cycle : NATURAL;
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80 clk0_multiply_by : NATURAL;
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81 invalid_lock_multiplier : NATURAL;
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82 inclk0_input_frequency : NATURAL;
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83 gate_lock_signal : STRING;
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84 clk0_divide_by : NATURAL;
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86 valid_lock_multiplier : NATURAL;
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87 clk0_time_delay : STRING;
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88 spread_frequency : NATURAL;
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89 intended_device_family : STRING;
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90 operation_mode : STRING;
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91 compensate_clock : STRING;
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92 clk0_phase_shift : STRING
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95 clkena : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
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96 inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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97 pllena : IN STD_LOGIC ;
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98 extclkena : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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99 locked : OUT STD_LOGIC ;
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100 areset : IN STD_LOGIC ;
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101 clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
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106 sub_wire3_bv(0 DOWNTO 0) <= "0";
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107 sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
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108 sub_wire5_bv(0 DOWNTO 0) <= "0";
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109 sub_wire5 <= NOT(To_stdlogicvector(sub_wire5_bv));
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110 sub_wire1 <= sub_wire0(0);
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112 locked <= sub_wire2;
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113 sub_wire4 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire5(0 DOWNTO 0);
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114 sub_wire6 <= inclk0;
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115 sub_wire7 <= sub_wire3(0 DOWNTO 0) & sub_wire6;
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116 sub_wire8 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0);
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121 altpll_component : altpll
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123 bandwidth_type => "AUTO",
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124 clk0_duty_cycle => 50,
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125 lpm_type => "altpll",
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126 clk0_multiply_by => 5435,
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127 invalid_lock_multiplier => 5,
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128 inclk0_input_frequency => 30003,
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129 gate_lock_signal => "NO",
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130 clk0_divide_by => 6666,
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131 pll_type => "AUTO",
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132 valid_lock_multiplier => 1,
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133 clk0_time_delay => "0",
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134 spread_frequency => 0,
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135 intended_device_family => "Stratix",
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136 operation_mode => "NORMAL",
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137 compensate_clock => "CLK0",
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138 clk0_phase_shift => "0"
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141 clkena => sub_wire4,
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142 inclk => sub_wire7,
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143 pllena => pllena_int,
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144 extclkena => sub_wire8,
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145 areset => areset_int,
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147 locked => sub_wire2
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154 -- ============================================================
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155 -- CNX file retrieval info
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156 -- ============================================================
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157 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
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158 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
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159 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
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160 -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
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161 -- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
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162 -- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
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163 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
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164 -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
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165 -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
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166 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
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167 -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
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168 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
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169 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
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170 -- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
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171 -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
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172 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
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173 -- Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
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174 -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
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175 -- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
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176 -- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
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177 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
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178 -- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
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179 -- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
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180 -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
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181 -- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
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182 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
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183 -- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
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184 -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
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185 -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
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186 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
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187 -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
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188 -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
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189 -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "33.330"
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190 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
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191 -- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
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192 -- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
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193 -- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
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194 -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
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195 -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
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196 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
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197 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
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198 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
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199 -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
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200 -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
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201 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
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202 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
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203 -- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
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204 -- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
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205 -- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
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206 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "299.970"
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207 -- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
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208 -- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
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209 -- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1"
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210 -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.330"
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211 -- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
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212 -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
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213 -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "27.175"
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214 -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
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215 -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
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216 -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
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217 -- Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix"
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218 -- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
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219 -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
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220 -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
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221 -- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
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222 -- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
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223 -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
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224 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
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225 -- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
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226 -- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
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227 -- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
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228 -- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "9"
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229 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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230 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
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231 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
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232 -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
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233 -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5435"
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234 -- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
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235 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30003"
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236 -- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
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237 -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6666"
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238 -- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
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239 -- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
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240 -- Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
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241 -- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
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242 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
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243 -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
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244 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
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245 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
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246 -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
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247 -- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
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248 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
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249 -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
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250 -- Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena"
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251 -- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
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252 -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]"
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253 -- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
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254 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
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255 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
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256 -- Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0
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257 -- Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0
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258 -- Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0
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259 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
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260 -- Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0
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261 -- Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0
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262 -- Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0
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263 -- Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0
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264 -- Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0
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265 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
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266 -- Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0
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267 -- Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
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268 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
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269 -- Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
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270 -- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.vhd TRUE FALSE
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271 -- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.inc FALSE FALSE
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272 -- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.cmp TRUE FALSE
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273 -- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.bsf TRUE
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274 -- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd TRUE FALSE
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