1 -------------------------------------------------------------------------------
2 -- Title : vga_driver entity
3 -- Project : LU Digital Design
4 -------------------------------------------------------------------------------
5 -- File : vga_driver_ent.vhd
6 -- Author : Thomas Handl
8 -- Created : 2004-12-15
9 -- Last update: 2006-02-24
10 -------------------------------------------------------------------------------
11 -- Description: generate vsync and hsync
12 -------------------------------------------------------------------------------
13 -- Copyright (c) 2004 TU Wien
14 -------------------------------------------------------------------------------
16 -- Date Version Author Description
17 -- 2004-12-15 1.0 handl Created
18 -- 2006-02-24 2.0 ST revised
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21 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
26 use IEEE.std_logic_1164.all;
27 use IEEE.std_logic_unsigned.all;
28 use IEEE.std_logic_arith.all;
32 -------------------------------------------------------------------------------
34 -------------------------------------------------------------------------------
38 port(clk : in std_logic;
40 column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);
41 line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
42 h_enable : out std_logic;
43 v_enable : out std_logic;
44 hsync, vsync : out std_logic;
46 d_hsync_state : out hsync_state_type;
47 d_vsync_state : out vsync_state_type;
48 d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
49 d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
50 d_set_hsync_counter : out std_logic;
51 d_set_vsync_counter : out std_logic;
52 d_set_column_counter : out std_logic;
53 d_set_line_counter : out std_logic
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