1 coreboot-4.0-2025-gabda90c-dirty Wed Feb 8 14:02:19 CET 2012 starting...
\r
3 BSP Family_Model: 00100fa0
\r
4 *sysinfo range: [000cc000,000cf360]
\r
6 cpu_init_detectedx = 00000000
\r
7 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000
\r
8 microcode: patch id to apply = 0x010000bf
\r
9 microcode: updated to patch id = 0x010000bf success
\r
17 SB900 - Early.c - get_sbdn - Start.
\r
18 SB900 - Early.c - get_sbdn - End.
\r
19 cpuSetAMDPCI 00 done
\r
20 Prep FID/VID Node:00
\r
21 P-state info in MSRC001_0064 is invalid !!!
\r
22 P-state info in MSRc0010064 is invalid !!!
\r
31 init node: 00 cores: 05
\r
32 Start other core - nodeid: 00 cores: 05
\r
34 started ap apicid: PPPPOOPOOSSSSOTSTTT::T:: :0 000xxx0xx3333300000
\r\r\r\r\r
39 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000051423 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000013245}}}}} ---------------
\r\r\r\r\r
44 * AmmmmmPiiiiicc cccrrrr0ro1oooocccccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000
\r\r\r\r\r
49 startmemmmmiiiidi
\rcccccrr
50 rrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff
\r\r\r\r\r
55 mmm*mmiiiii cAccccrrrPrrooooo c0ccccooo2oodddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss
\r\r\r\r\r
65 scccctpppcuppauuSSSuurSteeeSteeettAAAttdA
\rMMMADMM
66 DDMMMDDMSSSMRSSRR RR * AP 0 3dddddooooonnnnneeeee
\r\r\r\r\r
71 stiiiiinnnnnaiiriiitttttte_____ffdfffiiii
\ri
72 dddddvvvvviiiiiddddd_____aaaaappppp(((((ssssstttttaaaaagggggeeeee11111))))) aaaaapppppiiiiiccccciiiiiddddd::::: 0000032415
\r\r\r\r\r
77 FFF*FFIIIII DADDDDVVVPVVIIIII D0DDDD 4 ooooonnnnn AAAAAPPPPP::::: 0000015324
\r\r\r\r\r
87 fam10_optimization()
\r
90 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440
\r
92 FIDVID on BSP, APIC_id: 00
\r
94 Wait for AP stage 1: ap_apicid = 1
\r
96 common_fid(packed) = 0
\r
97 Wait for AP stage 1: ap_apicid = 2
\r
99 common_fid(packed) = 0
\r
100 Wait for AP stage 1: ap_apicid = 3
\r
102 common_fid(packed) = 0
\r
103 Wait for AP stage 1: ap_apicid = 4
\r
105 common_fid(packed) = 0
\r
106 Wait for AP stage 1: ap_apicid = 5
\r
108 common_fid(packed) = 0
\r
111 End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440
\r
112 rs780_htinit cpu_ht_freq=b.
\r
113 rs780_htinit: HT3 mode
\r
119 coreboot-4.0-2025-gabda90c-dirty Wed Feb 8 14:02:19 CET 2012 starting...
\r
121 BSP Family_Model: 00100fa0
\r
122 *sysinfo range: [000cc000,000cf360]
\r
124 cpu_init_detectedx = 00000000
\r
125 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000
\r
126 microcode: patch id to apply = 0x010000bf
\r
127 microcode: updated to patch id = 0x010000bf success
\r
132 Enter amd_ht_init()
\r
135 SB900 - Early.c - get_sbdn - Start.
\r
136 SB900 - Early.c - get_sbdn - End.
\r
137 cpuSetAMDPCI 00 done
\r
138 Prep FID/VID Node:00
\r
139 P-state info in MSRC001_0064 is invalid !!!
\r
140 P-state info in MSRc0010064 is invalid !!!
\r
148 start_other_cores()
\r
149 init node: 00 cores: 05
\r
150 Start other core - nodeid: 00 cores: 05
\r
152 started ap apicid: PPPPPOOOOOSSSSSTTTTT::::: 00000xxxxx3333300000
\r\r\r\r\r
157 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000015234 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000024351}}}}} ---------------
\r\r\r\r\r
162 * AmmmmmiPiiii cccccrrrrr0oooo1occcccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000
\r\r\r\r\r
167 startmmemmmiiidiiccc
\rccrr
168 rrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff
\r\r\r\r\r
173 mm*mmm iiiiicccccArrrrrPoooo occc0ccooo2oodddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss
\r\r\r\r\r
183 sccppccctupppauuuurSSSSSteeeeettetdAAttA
\rMMAA
184 DDMMMMMDDDMSSMMSSRRSRRR * AP 0 3dddddooooonnnnneeeee
\r\r\r\r\r
189 stiiiiannnniiiiinrttttit___te_ff_dffif
\riiidi
190 ddddvvvviviiidddid____ds_sssttsttaaaataggggegeeee22222 aa aapppapiiiipciccciiciiddddid:::: : 000 045230
\r1
\r\r\r
199 rs780_early_setup()
\r
200 fam10_optimization()
\r
203 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440
\r
206 End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440
\r
207 rs780_htinit cpu_ht_freq=b.
\r
208 rs780_htinit: HT3 mode
\r
213 raminit_amdmct begin:
\r
214 DIMMPresence: DIMMValid=c
\r
215 DIMMPresence: DIMMPresent=c
\r
216 DIMMPresence: RegDIMMPresent=0
\r
217 DIMMPresence: DimmECCPresent=0
\r
218 DIMMPresence: DimmPARPresent=0
\r
219 DIMMPresence: Dimmx4Present=0
\r
220 DIMMPresence: Dimmx8Present=c
\r
221 DIMMPresence: Dimmx16Present=0
\r
222 DIMMPresence: DimmPlPresent=0
\r
223 DIMMPresence: DimmDRPresent=c
\r
224 DIMMPresence: DimmQRPresent=0
\r
225 DIMMPresence: DATAload[0]=2
\r
226 DIMMPresence: MAload[0]=10
\r
227 DIMMPresence: MAdimms[0]=1
\r
228 DIMMPresence: DATAload[1]=2
\r
229 DIMMPresence: MAload[1]=10
\r
230 DIMMPresence: MAdimms[1]=1
\r
231 DIMMPresence: Status 1000
\r
232 DIMMPresence: ErrStatus 0
\r
233 DIMMPresence: ErrCode 0
\r
236 DCTInit_D: mct_DIMMPresence Done
\r
237 SPDCalcWidth: Status 1000
\r
238 SPDCalcWidth: ErrStatus 0
\r
239 SPDCalcWidth: ErrCode 0
\r
241 DCTInit_D: mct_SPDCalcWidth Done
\r
242 SPDGetTCL_D: DIMMCASL 4
\r
243 SPDGetTCL_D: DIMMAutoSpeed 4
\r
244 SPDGetTCL_D: Status 1000
\r
245 SPDGetTCL_D: ErrStatus 0
\r
246 SPDGetTCL_D: ErrCode 0
\r
249 AutoCycTiming: Status 1000
\r
250 AutoCycTiming: ErrStatus 0
\r
251 AutoCycTiming: ErrCode 0
\r
252 AutoCycTiming: Done
\r
254 DCTInit_D: AutoCycTiming_D Done
\r
255 SPDSetBanks: CSPresent c
\r
256 SPDSetBanks: Status 1000
\r
257 SPDSetBanks: ErrStatus 0
\r
258 SPDSetBanks: ErrCode 0
\r
261 AfterStitch pDCTstat->NodeSysBase = 0
\r
262 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff
\r
263 StitchMemory: Status 1000
\r
264 StitchMemory: ErrStatus 0
\r
265 StitchMemory: ErrCode 0
\r
268 InterleaveBanks_D: Status 1000
\r
269 InterleaveBanks_D: ErrStatus 0
\r
270 InterleaveBanks_D: ErrCode 0
\r
271 InterleaveBanks_D: Done
\r
273 AutoConfig_D: DramControl: 2a06
\r
274 AutoConfig_D: DramTimingLo: 90092
\r
275 AutoConfig_D: DramConfigMisc: 0
\r
276 AutoConfig_D: DramConfigMisc2: 0
\r
277 AutoConfig_D: DramConfigLo: 10000
\r
278 AutoConfig_D: DramConfigHi: f40000b
\r
279 AutoConfig: Status 1000
\r
280 AutoConfig: ErrStatus 0
\r
281 AutoConfig: ErrCode 0
\r
284 DCTInit_D: AutoConfig_D Done
\r
285 DCTInit_D: PlatformSpec_D Done
\r
286 DCTInit_D: StartupDCT_D
\r
287 DCTInit_D: mct_DIMMPresence Done
\r
288 SPDCalcWidth: Status 1000
\r
289 SPDCalcWidth: ErrStatus 0
\r
290 SPDCalcWidth: ErrCode 0
\r
292 DCTInit_D: mct_SPDCalcWidth Done
\r
293 AutoCycTiming: Status 1000
\r
294 AutoCycTiming: ErrStatus 0
\r
295 AutoCycTiming: ErrCode 0
\r
296 AutoCycTiming: Done
\r
298 DCTInit_D: AutoCycTiming_D Done
\r
299 SPDSetBanks: CSPresent c
\r
300 SPDSetBanks: Status 1000
\r
301 SPDSetBanks: ErrStatus 0
\r
302 SPDSetBanks: ErrCode 0
\r
305 AfterStitch pDCTstat->NodeSysBase = 0
\r
306 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe
\r
307 StitchMemory: Status 1000
\r
308 StitchMemory: ErrStatus 0
\r
309 StitchMemory: ErrCode 0
\r
312 InterleaveBanks_D: Status 1000
\r
313 InterleaveBanks_D: ErrStatus 0
\r
314 InterleaveBanks_D: ErrCode 0
\r
315 InterleaveBanks_D: Done
\r
317 AutoConfig_D: DramControl: 2a06
\r
318 AutoConfig_D: DramTimingLo: 90092
\r
319 AutoConfig_D: DramConfigMisc: 0
\r
320 AutoConfig_D: DramConfigMisc2: 0
\r
321 AutoConfig_D: DramConfigLo: 10000
\r
322 AutoConfig_D: DramConfigHi: f40000b
\r
323 AutoConfig: Status 1000
\r
324 AutoConfig: ErrStatus 0
\r
325 AutoConfig: ErrCode 0
\r
328 DCTInit_D: AutoConfig_D Done
\r
329 DCTInit_D: PlatformSpec_D Done
\r
330 DCTInit_D: StartupDCT_D
\r
331 mctAutoInitMCT_D: SyncDCTsReady_D
\r
332 mctAutoInitMCT_D: HTMemMapInit_D
\r
333 Node: 00 base: 00 limit: 1ffffff BottomIO: c00000
\r
334 Node: 00 base: 03 limit: 23fffff
\r
335 Node: 01 base: 00 limit: 00
\r
336 Node: 02 base: 00 limit: 00
\r
337 Node: 03 base: 00 limit: 00
\r
338 Node: 04 base: 00 limit: 00
\r
339 Node: 05 base: 00 limit: 00
\r
340 Node: 06 base: 00 limit: 00
\r
341 Node: 07 base: 00 limit: 00
\r
342 mctAutoInitMCT_D: CPUMemTyping_D
\r
343 CPUMemTyping: Cache32bTOP:c00000
\r
344 CPUMemTyping: Bottom32bIO:c00000
\r
345 CPUMemTyping: Bottom40bIO:2400000
\r
346 mctAutoInitMCT_D: DQSTiming_D
\r
347 TrainRcvrEn: Status 1100
\r
348 TrainRcvrEn: ErrStatus 0
\r
349 TrainRcvrEn: ErrCode 0
\r
352 TrainDQSRdWrPos: Status 1100
\r
353 TrainDQSRdWrPos: TrainErrors 0
\r
354 TrainDQSRdWrPos: ErrStatus 0
\r
355 TrainDQSRdWrPos: ErrCode 0
\r
356 TrainDQSRdWrPos: Done
\r
358 TrainDQSRdWrPos: Status 1100
\r
359 TrainDQSRdWrPos: TrainErrors 0
\r
360 TrainDQSRdWrPos: ErrStatus 0
\r
361 TrainDQSRdWrPos: ErrCode 0
\r
362 TrainDQSRdWrPos: Done
\r
364 TrainDQSRdWrPos: Status 1100
\r
365 TrainDQSRdWrPos: TrainErrors 0
\r
366 TrainDQSRdWrPos: ErrStatus 0
\r
367 TrainDQSRdWrPos: ErrCode 0
\r
368 TrainDQSRdWrPos: Done
\r
370 TrainDQSRdWrPos: Status 1100
\r
371 TrainDQSRdWrPos: TrainErrors 0
\r
372 TrainDQSRdWrPos: ErrStatus 0
\r
373 TrainDQSRdWrPos: ErrCode 0
\r
374 TrainDQSRdWrPos: Done
\r
376 mctAutoInitMCT_D: UMAMemTyping_D
\r
377 mctAutoInitMCT_D: :OtherTiming
\r
378 InterleaveNodes_D: Status 1100
\r
379 InterleaveNodes_D: ErrStatus 0
\r
380 InterleaveNodes_D: ErrCode 0
\r
381 InterleaveNodes_D: Done
\r
383 InterleaveChannels_D: Node 0
\r
384 InterleaveChannels_D: Status 1100
\r
385 InterleaveChannels_D: ErrStatus 0
\r
386 InterleaveChannels_D: ErrCode 0
\r
387 InterleaveChannels_D: Node 1
\r
388 InterleaveChannels_D: Status 1000
\r
389 InterleaveChannels_D: ErrStatus 0
\r
390 InterleaveChannels_D: ErrCode 0
\r
391 InterleaveChannels_D: Node 2
\r
392 InterleaveChannels_D: Status 1000
\r
393 InterleaveChannels_D: ErrStatus 0
\r
394 InterleaveChannels_D: ErrCode 0
\r
395 InterleaveChannels_D: Node 3
\r
396 InterleaveChannels_D: Status 1000
\r
397 InterleaveChannels_D: ErrStatus 0
\r
398 InterleaveChannels_D: ErrCode 0
\r
399 InterleaveChannels_D: Node 4
\r
400 InterleaveChannels_D: Status 1000
\r
401 InterleaveChannels_D: ErrStatus 0
\r
402 InterleaveChannels_D: ErrCode 0
\r
403 InterleaveChannels_D: Node 5
\r
404 InterleaveChannels_D: Status 1000
\r
405 InterleaveChannels_D: ErrStatus 0
\r
406 InterleaveChannels_D: ErrCode 0
\r
407 InterleaveChannels_D: Node 6
\r
408 InterleaveChannels_D: Status 1000
\r
409 InterleaveChannels_D: ErrStatus 0
\r
410 InterleaveChannels_D: ErrCode 0
\r
411 InterleaveChannels_D: Node 7
\r
412 InterleaveChannels_D: Status 1000
\r
413 InterleaveChannels_D: ErrStatus 0
\r
414 InterleaveChannels_D: ErrCode 0
\r
415 InterleaveChannels_D: Done
\r
417 mctAutoInitMCT_D: ECCInit_D
\r
419 raminit_amdmct end:
\r
424 Copying data from cache to RAM -- switching to use RAM as stack... Done
\r
426 Disabling cache as ram now
\r
427 Clearing initial memory region: Done
\r
429 Searching for fallback/coreboot_ram
\r
430 Check cmos_layout.bin
\r
431 Check fallback/romstage
\r
432 Check fallback/coreboot_ram
\r
433 Stage: loading fallback/coreboot_ram @ 0x200000 (1277952 bytes), entry @ 0x200000
\r
434 Stage: done loading.
\r
438 coreboot-4.0-2025-gabda90c-dirty Wed Feb 8 14:02:19 CET 2012 booting...
\r
440 Enumerating buses...
\r
441 Show all devs...Before device enumeration.
\r
442 Root Device: enabled 1
\r
443 APIC_CLUSTER: 0: enabled 1
\r
444 APIC: 00: enabled 1
\r
445 PCI_DOMAIN: 0000: enabled 1
\r
446 PCI: 00:18.0: enabled 1
\r
447 PCI: 00:00.0: enabled 1
\r
448 PCI: 00:02.0: enabled 1
\r
449 PCI: 00:03.0: enabled 0
\r
450 PCI: 00:04.0: enabled 1
\r
451 PCI: 00:05.0: enabled 0
\r
452 PCI: 00:06.0: enabled 0
\r
453 PCI: 00:07.0: enabled 0
\r
454 PCI: 00:08.0: enabled 0
\r
455 PCI: 00:09.0: enabled 1
\r
456 PCI: 00:0a.0: enabled 1
\r
457 PCI: 00:11.0: enabled 1
\r
458 PCI: 00:12.0: enabled 1
\r
459 PCI: 00:12.2: enabled 1
\r
460 PCI: 00:13.0: enabled 1
\r
461 PCI: 00:13.2: enabled 1
\r
462 PCI: 00:14.0: enabled 1
\r
463 I2C: 00:50: enabled 1
\r
464 I2C: 00:51: enabled 1
\r
465 I2C: 00:52: enabled 1
\r
466 I2C: 00:53: enabled 1
\r
467 PCI: 00:14.1: enabled 1
\r
468 PCI: 00:14.2: enabled 1
\r
469 PCI: 00:14.3: enabled 1
\r
470 PNP: 002e.0: enabled 0
\r
471 PNP: 002e.1: enabled 0
\r
472 PNP: 002e.2: enabled 1
\r
473 PNP: 002e.3: enabled 1
\r
474 PNP: 002e.5: enabled 1
\r
475 PNP: 002e.6: enabled 0
\r
476 PNP: 002e.7: enabled 0
\r
477 PNP: 002e.8: enabled 0
\r
478 PNP: 002e.9: enabled 0
\r
479 PNP: 002e.a: enabled 0
\r
480 PNP: 002e.b: enabled 1
\r
481 PCI: 00:14.4: enabled 0
\r
482 PCI: 00:14.5: enabled 1
\r
483 PCI: 00:14.6: enabled 0
\r
484 PCI: 00:15.0: enabled 1
\r
485 PCI: 00:15.1: enabled 1
\r
486 PCI: 00:15.2: enabled 1
\r
487 PCI: 00:15.3: enabled 1
\r
488 PCI: 00:16.0: enabled 1
\r
489 PCI: 00:16.2: enabled 1
\r
490 PCI: 00:18.1: enabled 1
\r
491 PCI: 00:18.2: enabled 1
\r
492 PCI: 00:18.3: enabled 1
\r
493 PCI: 00:18.4: enabled 1
\r
494 Compare with tree...
\r
495 Root Device: enabled 1
\r
496 APIC_CLUSTER: 0: enabled 1
\r
497 APIC: 00: enabled 1
\r
498 PCI_DOMAIN: 0000: enabled 1
\r
499 PCI: 00:18.0: enabled 1
\r
500 PCI: 00:00.0: enabled 1
\r
501 PCI: 00:02.0: enabled 1
\r
502 PCI: 00:03.0: enabled 0
\r
503 PCI: 00:04.0: enabled 1
\r
504 PCI: 00:05.0: enabled 0
\r
505 PCI: 00:06.0: enabled 0
\r
506 PCI: 00:07.0: enabled 0
\r
507 PCI: 00:08.0: enabled 0
\r
508 PCI: 00:09.0: enabled 1
\r
509 PCI: 00:0a.0: enabled 1
\r
510 PCI: 00:11.0: enabled 1
\r
511 PCI: 00:12.0: enabled 1
\r
512 PCI: 00:12.2: enabled 1
\r
513 PCI: 00:13.0: enabled 1
\r
514 PCI: 00:13.2: enabled 1
\r
515 PCI: 00:14.0: enabled 1
\r
516 I2C: 00:50: enabled 1
\r
517 I2C: 00:51: enabled 1
\r
518 I2C: 00:52: enabled 1
\r
519 I2C: 00:53: enabled 1
\r
520 PCI: 00:14.1: enabled 1
\r
521 PCI: 00:14.2: enabled 1
\r
522 PCI: 00:14.3: enabled 1
\r
523 PNP: 002e.0: enabled 0
\r
524 PNP: 002e.1: enabled 0
\r
525 PNP: 002e.2: enabled 1
\r
526 PNP: 002e.3: enabled 1
\r
527 PNP: 002e.5: enabled 1
\r
528 PNP: 002e.6: enabled 0
\r
529 PNP: 002e.7: enabled 0
\r
530 PNP: 002e.8: enabled 0
\r
531 PNP: 002e.9: enabled 0
\r
532 PNP: 002e.a: enabled 0
\r
533 PNP: 002e.b: enabled 1
\r
534 PCI: 00:14.4: enabled 0
\r
535 PCI: 00:14.5: enabled 1
\r
536 PCI: 00:14.6: enabled 0
\r
537 PCI: 00:15.0: enabled 1
\r
538 PCI: 00:15.1: enabled 1
\r
539 PCI: 00:15.2: enabled 1
\r
540 PCI: 00:15.3: enabled 1
\r
541 PCI: 00:16.0: enabled 1
\r
542 PCI: 00:16.2: enabled 1
\r
543 PCI: 00:18.1: enabled 1
\r
544 PCI: 00:18.2: enabled 1
\r
545 PCI: 00:18.3: enabled 1
\r
546 PCI: 00:18.4: enabled 1
\r
547 Mainboard ASUS M5A99X-EVO Enable. dev=0x0023257c
\r
548 m5a99x_evo_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
\r
549 m5a99x_evo_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000002
\r
550 m5a99x_evo_enable: uma size 0x10000000, memory start 0xb0000000
\r
551 m5a99x_evo_enable, w00t?!
\r
552 m5a99x_evo_enable, cya enable?!
\r
553 Enumerating buses... starting with root now
\r
554 scan_static_bus for Root Device
\r
555 APIC_CLUSTER: 0 enabled
\r
556 PCI_DOMAIN: 0000 enabled
\r
557 APIC_CLUSTER: 0 scanning...
\r
558 cpu_bus_scan: starting...
\r
559 PCI: 00:18.3 siblings=5
\r
560 CPU: APIC: 00 enabled
\r
561 CPU: APIC: 01 enabled
\r
562 CPU: APIC: 02 enabled
\r
563 CPU: APIC: 03 enabled
\r
564 CPU: APIC: 04 enabled
\r
565 CPU: APIC: 05 enabled
\r
566 cpu_bus_scan: done.
\r
567 PCI_DOMAIN: 0000 scanning...
\r
568 PCI: pci_scan_bus for bus 00
\r
570 pci_scan_bus: before pci_scan_get_dev! devfn: 192
\r
571 pci_scan_bus: after pci_scan_get_dev!
\r
572 pci_scan_bus: before pci_probe_dev!
\r
573 PCI: 00:18.0 [1022/1200] bus ops
\r
574 PCI: 00:18.0 [1022/1200] enabled
\r
575 pci_scan_bus: after pci_probe_dev!
\r
576 pci_scan_bus: before pci_scan_get_dev! devfn: 193
\r
577 pci_scan_bus: after pci_scan_get_dev!
\r
578 pci_scan_bus: before pci_probe_dev!
\r
579 PCI: 00:18.1 [1022/1201] enabled
\r
580 pci_scan_bus: after pci_probe_dev!
\r
581 pci_scan_bus: before pci_scan_get_dev! devfn: 194
\r
582 pci_scan_bus: after pci_scan_get_dev!
\r
583 pci_scan_bus: before pci_probe_dev!
\r
584 PCI: 00:18.2 [1022/1202] enabled
\r
585 pci_scan_bus: after pci_probe_dev!
\r
586 pci_scan_bus: before pci_scan_get_dev! devfn: 195
\r
587 pci_scan_bus: after pci_scan_get_dev!
\r
588 pci_scan_bus: before pci_probe_dev!
\r
589 PCI: 00:18.3 [1022/1203] ops
\r
590 PCI: 00:18.3 [1022/1203] enabled
\r
591 pci_scan_bus: after pci_probe_dev!
\r
592 pci_scan_bus: before pci_scan_get_dev! devfn: 196
\r
593 pci_scan_bus: after pci_scan_get_dev!
\r
594 pci_scan_bus: before pci_probe_dev!
\r
595 PCI: 00:18.4 [1022/1204] enabled
\r
596 pci_scan_bus: after pci_probe_dev!
\r
597 pci_scan_bus: before pci_scan_get_dev! devfn: 197
\r
598 pci_scan_bus: after pci_scan_get_dev!
\r
599 pci_scan_bus: before pci_probe_dev!
\r
600 pci_scan_bus: after pci_probe_dev!
\r
601 pci_scan_bus: before pci_scan_get_dev! devfn: 198
\r
602 pci_scan_bus: after pci_scan_get_dev!
\r
603 pci_scan_bus: before pci_probe_dev!
\r
604 pci_scan_bus: after pci_probe_dev!
\r
605 pci_scan_bus: before pci_scan_get_dev! devfn: 199
\r
606 pci_scan_bus: after pci_scan_get_dev!
\r
607 pci_scan_bus: before pci_probe_dev!
\r
608 pci_scan_bus: after pci_probe_dev!
\r
609 pci_scan_bus: before pci_scan_get_dev! devfn: 200
\r
610 pci_scan_bus: after pci_scan_get_dev!
\r
611 pci_scan_bus: before pci_probe_dev!
\r
612 pci_scan_bus: after pci_probe_dev!
\r
613 pci_scan_bus: before pci_scan_get_dev! devfn: 208
\r
614 pci_scan_bus: after pci_scan_get_dev!
\r
615 pci_scan_bus: before pci_probe_dev!
\r
616 pci_scan_bus: after pci_probe_dev!
\r
617 pci_scan_bus: before pci_scan_get_dev! devfn: 216
\r
618 pci_scan_bus: after pci_scan_get_dev!
\r
619 pci_scan_bus: before pci_probe_dev!
\r
620 pci_scan_bus: after pci_probe_dev!
\r
621 pci_scan_bus: before pci_scan_get_dev! devfn: 224
\r
622 pci_scan_bus: after pci_scan_get_dev!
\r
623 pci_scan_bus: before pci_probe_dev!
\r
624 pci_scan_bus: after pci_probe_dev!
\r
625 pci_scan_bus: before pci_scan_get_dev! devfn: 232
\r
626 pci_scan_bus: after pci_scan_get_dev!
\r
627 pci_scan_bus: before pci_probe_dev!
\r
628 pci_scan_bus: after pci_probe_dev!
\r
629 pci_scan_bus: before pci_scan_get_dev! devfn: 240
\r
630 pci_scan_bus: after pci_scan_get_dev!
\r
631 pci_scan_bus: before pci_probe_dev!
\r
632 pci_scan_bus: after pci_probe_dev!
\r
633 pci_scan_bus: before pci_scan_get_dev! devfn: 248
\r
634 pci_scan_bus: after pci_scan_get_dev!
\r
635 pci_scan_bus: before pci_probe_dev!
\r
636 pci_scan_bus: after pci_probe_dev!
\r
638 amdfam10_scan_chains: starting...
\r
639 amdfam10_scan_chains: link: 002328f0
\r
640 amdfam10_scan_chain: starting...
\r
641 amdfam10_scan_chain: link_type: 0x00000007
\r
642 amdfam10_scan_chain: link_type: 0x00000007
\r
643 amdfam10_scan_chain: before get_ht_c_index
\r
644 amdfam10_scan_chain: after get_ht_c_index
\r
645 amdfam10_scan_chain: before set_config_map_reg
\r
646 amdfam10_scan_chain: after set_config_map_reg
\r
647 amdfam10_scan_chain: before hypertransport_scan_chain
\r
648 hypertransport_scan_chain: before ht_collapse_early_enumeration
\r
649 hypertransport_scan_chain: after ht_collapse_early_enumeration
\r
650 hypertransport_scan_chain: before ht_scan_get_devs
\r
651 hypertransport_scan_chain: after ht_scan_get_devs
\r
652 hypertransport_scan_chain: before pci_probe_dev
\r
653 PCI: Using configuration type 1
\r
654 rs780_enable: dev=00232b48, VID_DID=0x5a141002
\r
655 Bus-0, Dev-0, Fun-0.
\r
657 addr=e0000000,bus=0,devfn=40
\r
658 gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
\r
660 NB_PCI_REG84 = 3000095.
\r
661 NB_PCI_REG4C = 52042.
\r
663 PCI: 00:00.0 [1002/5a14] enabled
\r
664 hypertransport_scan_chain: after pci_probe_dev
\r
665 hypertransport_scan_chain: before ht_lookup_slave_capability
\r
666 Capability: type 0x08 @ 0xf0
\r
668 Capability: type 0x08 @ 0xf0
\r
669 Capability: type 0x08 @ 0xc4
\r
671 hypertransport_scan_chain: after ht_lookup_slave_capability
\r
672 hypertransport_scan_chain: end_of_chain. w00t!
\r
673 hypertransport_scan_chain: before pci_scan_bus!
\r
674 PCI: pci_scan_bus for bus 00
\r
675 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff
\r
676 PCI: pci_scan_bus upper limit too big. Using 0xff.
\r
678 pci_scan_bus: before pci_scan_get_dev! devfn: 0
\r
679 pci_scan_bus: after pci_scan_get_dev!
\r
680 pci_scan_bus: before pci_probe_dev!
\r
681 rs780_enable: dev=00232b48, VID_DID=0x5a141002
\r
682 Bus-0, Dev-0, Fun-0.
\r
684 gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
\r
686 NB_PCI_REG84 = 3000095.
\r
687 NB_PCI_REG4C = 52042.
\r
689 PCI: 00:00.0 [1002/5a14] enabled
\r
690 pci_scan_bus: after pci_probe_dev!
\r
691 pci_scan_bus: before pci_scan_get_dev! devfn: 1
\r
692 pci_scan_bus: after pci_scan_get_dev!
\r
693 pci_scan_bus: before pci_probe_dev!
\r
694 pci_scan_bus: after pci_probe_dev!
\r
695 pci_scan_bus: before pci_scan_get_dev! devfn: 2
\r
696 pci_scan_bus: after pci_scan_get_dev!
\r
697 pci_scan_bus: before pci_probe_dev!
\r
698 pci_scan_bus: after pci_probe_dev!
\r
699 pci_scan_bus: before pci_scan_get_dev! devfn: 3
\r
700 pci_scan_bus: after pci_scan_get_dev!
\r
701 pci_scan_bus: before pci_probe_dev!
\r
702 pci_scan_bus: after pci_probe_dev!
\r
703 pci_scan_bus: before pci_scan_get_dev! devfn: 4
\r
704 pci_scan_bus: after pci_scan_get_dev!
\r
705 pci_scan_bus: before pci_probe_dev!
\r
706 pci_scan_bus: after pci_probe_dev!
\r
707 pci_scan_bus: before pci_scan_get_dev! devfn: 5
\r
708 pci_scan_bus: after pci_scan_get_dev!
\r
709 pci_scan_bus: before pci_probe_dev!
\r
710 pci_scan_bus: after pci_probe_dev!
\r
711 pci_scan_bus: before pci_scan_get_dev! devfn: 6
\r
712 pci_scan_bus: after pci_scan_get_dev!
\r
713 pci_scan_bus: before pci_probe_dev!
\r
714 pci_scan_bus: after pci_probe_dev!
\r
715 pci_scan_bus: before pci_scan_get_dev! devfn: 7
\r
716 pci_scan_bus: after pci_scan_get_dev!
\r
717 pci_scan_bus: before pci_probe_dev!
\r
718 pci_scan_bus: after pci_probe_dev!
\r
719 pci_scan_bus: before pci_scan_get_dev! devfn: 8
\r
720 pci_scan_bus: after pci_scan_get_dev!
\r
721 pci_scan_bus: before pci_probe_dev!
\r
722 pci_scan_bus: after pci_probe_dev!
\r
724 PCI: Left over static devices:
\r
752 PCI: Check your devicetree.cb.
\r
753 PCI: pci_scan_bus returning with max=000
\r
755 hypertransport_scan_chain: after pci_scan_bus!
\r
756 amdfam10_scan_chain: after hypertransport_scan_chain
\r
757 amdfam10_scan_chain: before set_config_map_reg
\r
758 amdfam10_scan_chain: after set_config_map_reg
\r
759 amdfam10_scan_chain: before store_ht_c_conf_bus
\r
760 amdfam10_scan_chain: after store_ht_c_conf_bus
\r
761 amdfam10_scan_chain: done.
\r
762 amdfam10_scan_chains: link: 00278000
\r
763 amdfam10_scan_chains: link: 00278018
\r
764 amdfam10_scan_chains: link: 00278030
\r
765 amdfam10_scan_chains: link: 00278048
\r
766 amdfam10_scan_chains: link: 00278060
\r
767 amdfam10_scan_chains: link: 00278078
\r
768 amdfam10_scan_chains: link: 00278090
\r
769 amdfam10_scan_chains: link2: 002328f0
\r
770 amdfam10_scan_chains: link2: 00278000
\r
771 amdfam10_scan_chain: starting...
\r
772 amdfam10_scan_chain: link_type: 0x00000000
\r
773 amdfam10_scan_chains: link2: 00278018
\r
774 amdfam10_scan_chain: starting...
\r
775 amdfam10_scan_chain: link_type: 0x00000000
\r
776 amdfam10_scan_chains: link2: 00278030
\r
777 amdfam10_scan_chain: starting...
\r
778 amdfam10_scan_chain: link_type: 0x00000000
\r
779 amdfam10_scan_chains: link2: 00278048
\r
780 amdfam10_scan_chain: starting...
\r
781 amdfam10_scan_chains: link2: 00278060
\r
782 amdfam10_scan_chain: starting...
\r
783 amdfam10_scan_chain: link_type: 0x00000000
\r
784 amdfam10_scan_chains: link2: 00278078
\r
785 amdfam10_scan_chain: starting...
\r
786 amdfam10_scan_chain: link_type: 0x00000000
\r
787 amdfam10_scan_chains: link2: 00278090
\r
788 amdfam10_scan_chain: starting...
\r
789 amdfam10_scan_chain: link_type: 0x00000000
\r
790 amdfam10_scan_chains: done.
\r
791 PCI: pci_scan_bus returning with max=000
\r
793 PCI_DOMAIN: 0000 passpw: enabled
\r
794 scan_static_bus for Root Device done
\r
797 ===============Enumeration done!========
\r
798 Allocating resources...
\r
799 Reading resources...
\r
800 Root Device read_resources bus 0 link: 0
\r
801 APIC_CLUSTER: 0 read_resources bus 0 link: 0
\r
802 APIC: 00 missing read_resources
\r
803 APIC: 01 missing read_resources
\r
804 APIC: 02 missing read_resources
\r
805 APIC: 03 missing read_resources
\r
806 APIC: 04 missing read_resources
\r
807 APIC: 05 missing read_resources
\r
808 APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
\r
809 PCI_DOMAIN: 0000 read_resources bus 0 link: 0
\r
810 PCI: 00:18.0 read_resources bus 0 link: 0
\r
811 PCI: 00:18.0 read_resources bus 0 link: 0 done
\r
812 PCI: 00:18.0 read_resources bus 0 link: 1
\r
813 PCI: 00:18.0 read_resources bus 0 link: 1 done
\r
814 PCI: 00:18.0 read_resources bus 0 link: 2
\r
815 PCI: 00:18.0 read_resources bus 0 link: 2 done
\r
816 PCI: 00:18.0 read_resources bus 0 link: 3
\r
817 PCI: 00:18.0 read_resources bus 0 link: 3 done
\r
818 PCI: 00:18.0 read_resources bus 0 link: 4
\r
819 PCI: 00:18.0 read_resources bus 0 link: 4 done
\r
820 PCI: 00:18.0 read_resources bus 0 link: 5
\r
821 PCI: 00:18.0 read_resources bus 0 link: 5 done
\r
822 PCI: 00:18.0 read_resources bus 0 link: 6
\r
823 PCI: 00:18.0 read_resources bus 0 link: 6 done
\r
824 PCI: 00:18.0 read_resources bus 0 link: 7
\r
825 PCI: 00:18.0 read_resources bus 0 link: 7 done
\r
826 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
\r
827 Root Device read_resources bus 0 link: 0 done
\r
828 Done reading resources.
\r
829 Show resources in subtree (Root Device)...After reading.
\r
830 Root Device child on link 0 APIC_CLUSTER: 0
\r
831 APIC_CLUSTER: 0 child on link 0 APIC: 00
\r
838 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0
\r
839 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
\r
840 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
\r
841 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
\r
842 PCI: 00:18.0 child on link 0 PCI: 00:00.0
\r
843 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b0
\r
844 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b8
\r
845 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8
\r
847 PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 201 index 1c
\r
851 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
\r
853 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
\r
854 PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
\r
855 PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
\r
856 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
\r
857 PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
\r
858 PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
\r
859 PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done
\r
860 PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
\r
861 PCI: 00:00.0 1c * [0x0 - 0xfffffff] mem
\r
862 PCI: 00:18.0 compute_resources_mem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffffff done
\r
863 PCI: 00:18.0 10b8 * [0x0 - 0xfffffff] mem
\r
864 PCI: 00:18.3 94 * [0x10000000 - 0x13ffffff] mem
\r
865 PCI_DOMAIN: 0000 compute_resources_mem: base: 14000000 size: 14000000 align: 28 gran: 0 limit: ffffffff done
\r
866 avoid_fixed_resources: PCI_DOMAIN: 0000
\r
867 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
\r
868 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
\r
869 constrain_resources: PCI_DOMAIN: 0000
\r
870 constrain_resources: PCI: 00:18.0
\r
871 constrain_resources: PCI: 00:00.0
\r
872 constrain_resources: PCI: 00:18.1
\r
873 constrain_resources: PCI: 00:18.2
\r
874 constrain_resources: PCI: 00:18.3
\r
875 constrain_resources: PCI: 00:18.4
\r
876 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
\r
877 lim->base 00000000 lim->limit 0000ffff
\r
878 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff
\r
879 lim->base 00000000 lim->limit dfffffff
\r
880 Setting resources...
\r
881 PCI_DOMAIN: 0000 allocate_resources_io: base:0 size:0 align:0 gran:0 limit:ffff
\r
882 PCI_DOMAIN: 0000 allocate_resources_io: next_base: 0 size: 0 align: 0 gran: 0 done
\r
883 PCI: 00:18.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
\r
884 PCI: 00:18.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
\r
885 PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:14000000 align:28 gran:0 limit:dfffffff
\r
886 Assigned: PCI: 00:18.0 10b8 * [0xc0000000 - 0xcfffffff] mem
\r
887 Assigned: PCI: 00:18.3 94 * [0xd0000000 - 0xd3ffffff] mem
\r
888 PCI_DOMAIN: 0000 allocate_resources_mem: next_base: d4000000 size: 14000000 align: 28 gran: 0 done
\r
889 PCI: 00:18.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
\r
890 PCI: 00:18.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
\r
891 PCI: 00:18.0 allocate_resources_mem: base:c0000000 size:10000000 align:28 gran:20 limit:dfffffff
\r
892 Assigned: PCI: 00:00.0 1c * [0xc0000000 - 0xcfffffff] mem
\r
893 PCI: 00:18.0 allocate_resources_mem: next_base: d0000000 size: 10000000 align: 28 gran: 20 done
\r
894 Root Device assign_resources, bus 0 link: 0
\r
895 split: 64K table at =afff0000
\r
896 0: mmio_basek=00300000, basek=00400000, limitk=00900000
\r
897 Adding UMA memory area
\r
898 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
\r
899 PCI: 00:18.0 10b0 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 prefmem <node 0 link 0>
\r
900 PCI: 00:18.0 10b8 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x14 mem <node 0 link 0>
\r
901 PCI: 00:18.0 10d8 <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c io <node 0 link 0>
\r
902 PCI: 00:18.0 assign_resources, bus 0 link: 0
\r
903 PCI: 00:00.0 1c <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c mem64
\r
904 PCI: 00:18.0 assign_resources, bus 0 link: 0
\r
905 PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem <gart>
\r
906 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
\r
907 Root Device assign_resources, bus 0 link: 0
\r
908 Done setting resources.
\r
909 Show resources in subtree (Root Device)...After assigning values.
\r
910 Root Device child on link 0 APIC_CLUSTER: 0
\r
911 APIC_CLUSTER: 0 child on link 0 APIC: 00
\r
918 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0
\r
919 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
\r
920 PCI_DOMAIN: 0000 resource base c0000000 size 14000000 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
\r
921 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
\r
922 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
\r
923 PCI_DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20
\r
924 PCI_DOMAIN: 0000 resource base 100000000 size 130000000 align 0 gran 0 limit 0 flags e0004200 index 30
\r
925 PCI_DOMAIN: 0000 resource base b0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 7
\r
926 PCI: 00:18.0 child on link 0 PCI: 00:00.0
\r
927 PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081200 index 10b0
\r
928 PCI: 00:18.0 resource base c0000000 size 10000000 align 28 gran 20 limit dfffffff flags 60080200 index 10b8
\r
929 PCI: 00:18.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080100 index 10d8
\r
931 PCI: 00:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60000201 index 1c
\r
935 PCI: 00:18.3 resource base d0000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94
\r
937 Done allocating resources.
\r
939 Enabling resources...
\r
940 PCI: 00:18.0 cmd <- 00
\r
941 PCI: 00:18.1 subsystem <- 1043/843e
\r
942 PCI: 00:18.1 cmd <- 00
\r
943 PCI: 00:18.2 subsystem <- 1043/843e
\r
944 PCI: 00:18.2 cmd <- 00
\r
945 PCI: 00:18.3 cmd <- 00
\r
946 PCI: 00:18.4 subsystem <- 1043/843e
\r
947 PCI: 00:18.4 cmd <- 00
\r
948 PCI: 00:00.0 subsystem <- 1043/843e
\r
949 PCI: 00:00.0 cmd <- 02
\r
951 Initializing devices...
\r
953 APIC_CLUSTER: 0 init
\r
954 start_eip=0x0000a000, offset=0x00200000, code_size=0x0000005b
\r
955 Initializing CPU #0
\r
956 CPU: vendor AMD device 100fa0
\r
957 CPU: family 10, model 0a, stepping 00
\r
958 nodeid = 00, coreid = 00
\r
962 Setting fixed MTRRs(0-88) type: UC
\r
963 Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
\r
964 Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
\r
966 Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.
\r
967 Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB
\r
968 ADDRESS_MASK_HIGH=0xffff
\r
969 Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB
\r
970 ADDRESS_MASK_HIGH=0xffff
\r
971 Setting variable MTRR 2, base: 8704MB, range: 256MB, type WB
\r
972 ADDRESS_MASK_HIGH=0xffff
\r
973 Setting variable MTRR 3, base: 3072MB, range: 1024MB, type UC
\r
974 ADDRESS_MASK_HIGH=0xffff
\r
975 DONE variable MTRRs
\r
976 Clear out the extra MTRR's
\r
977 call enable_var_mtrr()
\r
978 Leave x86_setup_var_mtrrs
\r
982 Fixed MTRRs : Enabled
\r
983 Variable MTRRs: Enabled
\r
986 Setting up local apic... apic_id: 0x00 done.
\r
988 CPU model: AMD Processor model unknown
\r
989 siblings = 05, CPU #0 initialized
\r
991 Waiting for send to finish...
\r
993 Waiting for send to finish...
\r
994 +#startup loops: 1.
\r
995 Sending STARTUP #1 to 1.
\r
998 Waiting for send to finish...
\r
1000 Initializing CPU #1
\r
1001 CPU: vendor AMD device 100fa0
\r
1002 CPU: family 10, model 0a, stepping 00
\r
1003 nodeid = 00, coreid = 01
\r
1007 Setting fixed MTRRs(0-88) type: UC
\r
1008 Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
\r
1009 Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
\r
1011 Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.
\r
1012 Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB
\r
1013 ADDRESS_MASK_HIGH=0xffff
\r
1014 Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB
\r
1015 ADDRESS_MASK_HIGH=0xffff
\r
1016 Setting variable MTRR 2, base: 8704MB, range: 256MB, type WB
\r
1017 ADDRESS_MASK_HIGH=0xffff
\r
1018 Setting variable MTRR 3, base: 3072MB, range: 1024MB, type UC
\r
1019 ADDRESS_MASK_HIGH=0xffff
\r
1020 DONE variable MTRRs
\r
1021 Clear out the extra MTRR's
\r
1022 call enable_var_mtrr()
\r
1023 Leave x86_setup_var_mtrrs
\r
1027 Fixed MTRRs : Enabled
\r
1028 Variable MTRRs: Enabled
\r
1031 Setting up local apic... apic_id: 0x01 done.
\r
1033 CPU model: AMD Processor model unknown
\r
1034 siblings = 05, CPU #1 initialized
\r
1036 Waiting for send to finish...
\r
1037 +Deasserting INIT.
\r
1038 Waiting for send to finish...
\r
1039 +#startup loops: 1.
\r
1040 Sending STARTUP #1 to 2.
\r
1043 Waiting for send to finish...
\r
1045 Initializing CPU #2
\r
1046 CPU: vendor AMD device 100fa0
\r
1047 CPU: family 10, model 0a, stepping 00
\r
1048 nodeid = 00, coreid = 02
\r
1052 Setting fixed MTRRs(0-88) type: UC
\r
1053 Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
\r
1054 Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
\r
1056 Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.
\r
1057 Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB
\r
1058 ADDRESS_MASK_HIGH=0xffff
\r
1059 Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB
\r
1060 ADDRESS_MASK_HIGH=0xffff
\r
1061 Setting variable MTRR 2, base: 8704MB, range: 256MB, type WB
\r
1062 ADDRESS_MASK_HIGH=0xffff
\r
1063 Setting variable MTRR 3, base: 3072MB, range: 1024MB, type UC
\r
1064 ADDRESS_MASK_HIGH=0xffff
\r
1065 DONE variable MTRRs
\r
1066 Clear out the extra MTRR's
\r
1067 call enable_var_mtrr()
\r
1068 Leave x86_setup_var_mtrrs
\r
1072 Fixed MTRRs : Enabled
\r
1073 Variable MTRRs: Enabled
\r
1076 Setting up local apic... apic_id: 0x02 done.
\r
1078 CPU model: AMD Processor model unknown
\r
1079 siblings = 05, CPU #2 initialized
\r
1081 Waiting for send to finish...
\r
1082 +Deasserting INIT.
\r
1083 Waiting for send to finish...
\r
1084 +#startup loops: 1.
\r
1085 Sending STARTUP #1 to 3.
\r
1088 Waiting for send to finish...
\r
1090 Initializing CPU #3
\r
1091 CPU: vendor AMD device 100fa0
\r
1092 CPU: family 10, model 0a, stepping 00
\r
1093 nodeid = 00, coreid = 03
\r
1097 Setting fixed MTRRs(0-88) type: UC
\r
1098 Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
\r
1099 Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
\r
1101 Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.
\r
1102 Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB
\r
1103 ADDRESS_MASK_HIGH=0xffff
\r
1104 Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB
\r
1105 ADDRESS_MASK_HIGH=0xffff
\r
1106 Setting variable MTRR 2, base: 8704MB, range: 256MB, type WB
\r
1107 ADDRESS_MASK_HIGH=0xffff
\r
1108 Setting variable MTRR 3, base: 3072MB, range: 1024MB, type UC
\r
1109 ADDRESS_MASK_HIGH=0xffff
\r
1110 DONE variable MTRRs
\r
1111 Clear out the extra MTRR's
\r
1112 call enable_var_mtrr()
\r
1113 Leave x86_setup_var_mtrrs
\r
1117 Fixed MTRRs : Enabled
\r
1118 Variable MTRRs: Enabled
\r
1121 Setting up local apic... apic_id: 0x03 done.
\r
1123 CPU model: AMD Processor model unknown
\r
1124 siblings = 05, CPU #3 initialized
\r
1126 Waiting for send to finish...
\r
1127 +Deasserting INIT.
\r
1128 Waiting for send to finish...
\r
1129 +#startup loops: 1.
\r
1130 Sending STARTUP #1 to 4.
\r
1133 Waiting for send to finish...
\r
1135 Initializing CPU #4
\r
1136 CPU: vendor AMD device 100fa0
\r
1137 CPU: family 10, model 0a, stepping 00
\r
1138 nodeid = 00, coreid = 04
\r
1142 Setting fixed MTRRs(0-88) type: UC
\r
1143 Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
\r
1144 Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
\r
1146 Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.
\r
1147 Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB
\r
1148 ADDRESS_MASK_HIGH=0xffff
\r
1149 Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB
\r
1150 ADDRESS_MASK_HIGH=0xffff
\r
1151 Setting variable MTRR 2, base: 8704MB, range: 256MB, type WB
\r
1152 ADDRESS_MASK_HIGH=0xffff
\r
1153 Setting variable MTRR 3, base: 3072MB, range: 1024MB, type UC
\r
1154 ADDRESS_MASK_HIGH=0xffff
\r
1155 DONE variable MTRRs
\r
1156 Clear out the extra MTRR's
\r
1157 call enable_var_mtrr()
\r
1158 Leave x86_setup_var_mtrrs
\r
1162 Fixed MTRRs : Enabled
\r
1163 Variable MTRRs: Enabled
\r
1166 Setting up local apic... apic_id: 0x04 done.
\r
1168 CPU model: AMD Processor model unknown
\r
1169 siblings = 05, CPU #4 initialized
\r
1171 Waiting for send to finish...
\r
1172 +Deasserting INIT.
\r
1173 Waiting for send to finish...
\r
1174 +#startup loops: 1.
\r
1175 Sending STARTUP #1 to 5.
\r
1178 Waiting for send to finish...
\r
1180 Initializing CPU #5
\r
1181 Waiting for 1 CPUS to stop
\r
1182 CPU: vendor AMD device 100fa0
\r
1183 CPU: family 10, model 0a, stepping 00
\r
1184 nodeid = 00, coreid = 05
\r
1188 Setting fixed MTRRs(0-88) type: UC
\r
1189 Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
\r
1190 Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
\r
1192 Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.
\r
1193 Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB
\r
1194 ADDRESS_MASK_HIGH=0xffff
\r
1195 Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB
\r
1196 ADDRESS_MASK_HIGH=0xffff
\r
1197 Setting variable MTRR 2, base: 8704MB, range: 256MB, type WB
\r
1198 ADDRESS_MASK_HIGH=0xffff
\r
1199 Setting variable MTRR 3, base: 3072MB, range: 1024MB, type UC
\r
1200 ADDRESS_MASK_HIGH=0xffff
\r
1201 DONE variable MTRRs
\r
1202 Clear out the extra MTRR's
\r
1203 call enable_var_mtrr()
\r
1204 Leave x86_setup_var_mtrrs
\r
1208 Fixed MTRRs : Enabled
\r
1209 Variable MTRRs: Enabled
\r
1212 Setting up local apic... apic_id: 0x05 done.
\r
1214 CPU model: AMD Processor model unknown
\r
1215 siblings = 05, CPU #5 initialized
\r
1216 All AP CPUs stopped
\r
1217 SB900 - Early.c - sb_After_Pci_Init - Start.
\r
1218 SB900 - Cfg.c - sb900_cimx_config - Start.
\r
1219 SB900 - Cfg.c - sb900_cimx_config - End.
\r
1220 SB900 - Early.c - sb_After_Pci_Init - End.
\r
1221 SB900 - Early.c - sb_Mid_Post_Init - Start.
\r
1222 SB900 - Cfg.c - sb900_cimx_config - Start.
\r
1223 SB900 - Cfg.c - sb900_cimx_config - End.
\r
1224 SB900 - Early.c - sb_Mid_Post_Init - End.
\r
1229 NB: Function 3 Misc Control.. done.
\r
1232 Devices initialized
\r
1233 Show all devs...After init.
\r
1234 Root Device: enabled 1
\r
1235 APIC_CLUSTER: 0: enabled 1
\r
1236 APIC: 00: enabled 1
\r
1237 PCI_DOMAIN: 0000: enabled 1
\r
1238 PCI: 00:18.0: enabled 1
\r
1239 PCI: 00:00.0: enabled 1
\r
1240 PCI: 00:02.0: enabled 1
\r
1241 PCI: 00:03.0: enabled 0
\r
1242 PCI: 00:04.0: enabled 1
\r
1243 PCI: 00:05.0: enabled 0
\r
1244 PCI: 00:06.0: enabled 0
\r
1245 PCI: 00:07.0: enabled 0
\r
1246 PCI: 00:08.0: enabled 0
\r
1247 PCI: 00:09.0: enabled 1
\r
1248 PCI: 00:0a.0: enabled 1
\r
1249 PCI: 00:11.0: enabled 1
\r
1250 PCI: 00:12.0: enabled 1
\r
1251 PCI: 00:12.2: enabled 1
\r
1252 PCI: 00:13.0: enabled 1
\r
1253 PCI: 00:13.2: enabled 1
\r
1254 PCI: 00:14.0: enabled 1
\r
1255 I2C: 00:50: enabled 1
\r
1256 I2C: 00:51: enabled 1
\r
1257 I2C: 00:52: enabled 1
\r
1258 I2C: 00:53: enabled 1
\r
1259 PCI: 00:14.1: enabled 1
\r
1260 PCI: 00:14.2: enabled 1
\r
1261 PCI: 00:14.3: enabled 1
\r
1262 PNP: 002e.0: enabled 0
\r
1263 PNP: 002e.1: enabled 0
\r
1264 PNP: 002e.2: enabled 1
\r
1265 PNP: 002e.3: enabled 1
\r
1266 PNP: 002e.5: enabled 1
\r
1267 PNP: 002e.6: enabled 0
\r
1268 PNP: 002e.7: enabled 0
\r
1269 PNP: 002e.8: enabled 0
\r
1270 PNP: 002e.9: enabled 0
\r
1271 PNP: 002e.a: enabled 0
\r
1272 PNP: 002e.b: enabled 1
\r
1273 PCI: 00:14.4: enabled 0
\r
1274 PCI: 00:14.5: enabled 1
\r
1275 PCI: 00:14.6: enabled 0
\r
1276 PCI: 00:15.0: enabled 1
\r
1277 PCI: 00:15.1: enabled 1
\r
1278 PCI: 00:15.2: enabled 1
\r
1279 PCI: 00:15.3: enabled 1
\r
1280 PCI: 00:16.0: enabled 1
\r
1281 PCI: 00:16.2: enabled 1
\r
1282 PCI: 00:18.1: enabled 1
\r
1283 PCI: 00:18.2: enabled 1
\r
1284 PCI: 00:18.3: enabled 1
\r
1285 PCI: 00:18.4: enabled 1
\r
1286 APIC: 01: enabled 1
\r
1287 APIC: 02: enabled 1
\r
1288 APIC: 03: enabled 1
\r
1289 APIC: 04: enabled 1
\r
1290 APIC: 05: enabled 1
\r
1292 Initializing CBMEM area to 0xafff0000 (65536 bytes)
\r
1293 Adding CBMEM entry as no. 1
\r
1294 Moving GDT to afff0200...ok
\r
1295 High Tables Base is afff0000.
\r
1297 SB900 - Early.c - sb_Late_Post - Start.
\r
1298 SB900 - Cfg.c - sb900_cimx_config - Start.
\r
1299 SB900 - Cfg.c - sb900_cimx_config - End.
\r
1300 SB900 - Early.c - sb_Late_Post - End.
\r
1301 Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
\r
1302 Adding CBMEM entry as no. 2
\r
1303 Writing IRQ routing tables to 0xafff0400...write_pirq_routing_table done.
\r
1304 PIRQ table: 48 bytes.
\r
1306 Wrote the mp table end at: 000f0410 - 000f0554
\r
1307 Adding CBMEM entry as no. 3
\r
1308 Wrote the mp table end at: afff1410 - afff1554
\r
1309 MP table: 340 bytes.
\r
1311 Adding CBMEM entry as no. 4
\r
1312 ACPI: Writing ACPI tables at afff2400...
\r
1313 ACPI: * HPET at afff24c8
\r
1314 ACPI: added table 1/32, length now 40
\r
1315 ACPI: * MADT at afff2500
\r
1316 ACPI: added table 2/32, length now 44
\r
1317 ACPI: * SRAT at afff2580
\r
1318 SRAT: lapic cpu_index=00, node_id=00, apic_id=00
\r
1319 SRAT: lapic cpu_index=01, node_id=00, apic_id=01
\r
1320 SRAT: lapic cpu_index=02, node_id=00, apic_id=02
\r
1321 SRAT: lapic cpu_index=03, node_id=00, apic_id=03
\r
1322 SRAT: lapic cpu_index=04, node_id=00, apic_id=04
\r
1323 SRAT: lapic cpu_index=05, node_id=00, apic_id=05
\r
1324 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
\r
1325 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
\r
1326 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00400000, sizek=004c0000
\r
1327 ACPI: added table 3/32, length now 48
\r
1328 ACPI: * SLIT at afff2688
\r
1329 ACPI: added table 4/32, length now 52
\r
1330 ACPI: * SSDT at afff26c0
\r
1331 ACPI: added table 5/32, length now 56
\r
1332 ACPI: * SSDT for PState at afff2cf5
\r
1333 ACPI: * DSDT at afff2cf8
\r
1334 ACPI: * DSDT @ afff2cf8 Length 288b
\r
1335 ACPI: * FACS at afff5588
\r
1336 ACPI: * FADT at afff55c8
\r
1337 ACPI_BLK_BASE: 0x0800
\r
1338 ACPI: added table 6/32, length now 60
\r
1340 ACPI tables: 12988 bytes.
\r
1341 Adding CBMEM entry as no. 5
\r
1342 smbios_write_tables: afffd800
\r
1343 Root Device (ASUS M5A99X-EVO Mainboard)
\r
1344 APIC_CLUSTER: 0 (AMD FAM10 Root Complex)
\r
1345 APIC: 00 (socket AM3)
\r
1346 PCI_DOMAIN: 0000 (AMD FAM10 Root Complex)
\r
1347 PCI: 00:18.0 (AMD FAM10 Northbridge)
\r
1348 PCI: 00:00.0 (ATI RS780)
\r
1349 PCI: 00:02.0 (ATI RS780)
\r
1350 PCI: 00:03.0 (ATI RS780)
\r
1351 PCI: 00:04.0 (ATI RS780)
\r
1352 PCI: 00:05.0 (ATI RS780)
\r
1353 PCI: 00:06.0 (ATI RS780)
\r
1354 PCI: 00:07.0 (ATI RS780)
\r
1355 PCI: 00:08.0 (ATI RS780)
\r
1356 PCI: 00:09.0 (ATI RS780)
\r
1357 PCI: 00:0a.0 (ATI RS780)
\r
1358 PCI: 00:11.0 (ATI SB900)
\r
1359 PCI: 00:12.0 (ATI SB900)
\r
1360 PCI: 00:12.2 (ATI SB900)
\r
1361 PCI: 00:13.0 (ATI SB900)
\r
1362 PCI: 00:13.2 (ATI SB900)
\r
1363 PCI: 00:14.0 (ATI SB900)
\r
1368 PCI: 00:14.1 (ATI SB900)
\r
1369 PCI: 00:14.2 (ATI SB900)
\r
1370 PCI: 00:14.3 (ATI SB900)
\r
1371 PNP: 002e.0 (ITE IT8721F Super I/O)
\r
1372 PNP: 002e.1 (ITE IT8721F Super I/O)
\r
1373 PNP: 002e.2 (ITE IT8721F Super I/O)
\r
1374 PNP: 002e.3 (ITE IT8721F Super I/O)
\r
1375 PNP: 002e.5 (ITE IT8721F Super I/O)
\r
1376 PNP: 002e.6 (ITE IT8721F Super I/O)
\r
1377 PNP: 002e.7 (ITE IT8721F Super I/O)
\r
1378 PNP: 002e.8 (ITE IT8721F Super I/O)
\r
1379 PNP: 002e.9 (ITE IT8721F Super I/O)
\r
1380 PNP: 002e.a (ITE IT8721F Super I/O)
\r
1381 PNP: 002e.b (ITE IT8721F Super I/O)
\r
1382 PCI: 00:14.4 (ATI SB900)
\r
1383 PCI: 00:14.5 (ATI SB900)
\r
1384 PCI: 00:14.6 (ATI SB900)
\r
1385 PCI: 00:15.0 (ATI SB900)
\r
1386 PCI: 00:15.1 (ATI SB900)
\r
1387 PCI: 00:15.2 (ATI SB900)
\r
1388 PCI: 00:15.3 (ATI SB900)
\r
1389 PCI: 00:16.0 (ATI SB900)
\r
1390 PCI: 00:16.2 (ATI SB900)
\r
1391 PCI: 00:18.1 (AMD FAM10 Northbridge)
\r
1392 PCI: 00:18.2 (AMD FAM10 Northbridge)
\r
1393 PCI: 00:18.3 (AMD FAM10 Northbridge)
\r
1394 PCI: 00:18.4 (AMD FAM10 Northbridge)
\r
1400 SMBIOS tables: 275 bytes.
\r
1402 Adding CBMEM entry as no. 6
\r
1403 Writing high table forward entry at 0x00000500
\r
1404 Wrote coreboot table at: 00000500 - 00000518 checksum 6fde
\r
1405 New low_table_end: 0x00000518
\r
1406 Now going to write high coreboot table at 0xafffe000
\r
1407 rom_table_end = 0xafffe000
\r
1408 Adjust low_table_end from 0x00000518 to 0x00001000
\r
1409 Adjust rom_table_end from 0xafffe000 to 0xb0000000
\r
1410 Adding high table area
\r
1411 uma_memory_start=0xb0000000, uma_memory_size=0x10000000
\r
1412 coreboot memory table:
\r
1413 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
\r
1414 1. 0000000000001000-000000000009ffff: RAM
\r
1415 2. 00000000000c0000-00000000affeffff: RAM
\r
1416 3. 00000000afff0000-00000000afffffff: CONFIGURATION TABLES
\r
1417 4. 00000000b0000000-00000000bfffffff: RESERVED
\r
1418 5. 00000000e0000000-00000000efffffff: RESERVED
\r
1419 6. 0000000100000000-000000022fffffff: RAM
\r
1420 Wrote coreboot table at: afffe000 - afffe1f8 checksum b7d4
\r
1421 coreboot table: 504 bytes.
\r
1424 Multiboot Information structure has been written.
\r
1425 0. FREE SPACE b0000000 00000000
\r
1426 1. GDT afff0200 00000200
\r
1427 2. IRQ TABLE afff0400 00001000
\r
1428 3. SMP TABLE afff1400 00001000
\r
1429 4. ACPI afff2400 0000b400
\r
1430 5. SMBIOS afffd800 00000800
\r
1431 6. COREBOOT afffe000 00002000
\r
1432 Searching for fallback/payload
\r
1433 Check cmos_layout.bin
\r
1434 Check fallback/romstage
\r
1435 Check fallback/coreboot_ram
\r
1436 Check fallback/payload
\r
1438 Loading segment from rom address 0xffc349f8
\r
1439 data (compression=1)
\r
1440 New segment dstaddr 0xe7e04 memsize 0x181fc srcaddr 0xffc34a30 filesize 0xc216
\r
1441 (cleaned up) New segment addr 0xe7e04 size 0x181fc offset 0xffc34a30 filesize 0xc216
\r
1442 Loading segment from rom address 0xffc34a14
\r
1443 Entry Point 0x00000000
\r
1444 Loading Segment: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c216
\r
1445 lb: [0x0000000000200000, 0x0000000000338000)
\r
1446 Post relocation: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c216
\r
1448 [ 0x000e7e04, 00100000, 0x00100000) <- ffc34a30
\r
1449 dest 000e7e04, end 00100000, bouncebuffer afd80000
\r
1451 Jumping to boot code at fc8c0
\r
1453 entry = 0x000fc8c0
\r
1454 lb_start = 0x00200000
\r
1455 lb_size = 0x00138000
\r
1456 adjust = 0xafcb8000
\r
1457 buffer = 0xafd80000
\r
1458 elf_boot_notes = 0x002337dc
\r
1459 adjusted_boot_notes = 0xafeeb7dc
\r
1460 Start bios (version 1.6.3-20120208_140307-oldx86)
\r
1461 Found mainboard ASUS M5A99X-EVO
\r
1462 Found CBFS header at 0xfffffca0
\r
1463 Ram Size=0xafff0000 (0x0000000130000000 high)
\r
1464 Relocating init from 0x000e8450 to 0xaffd57a0 (size 42812)
\r