1 coreboot-4.0-2002-gee77cf1-dirty Fri Feb 3 02:48:24 CET 2012 starting...
\r
3 BSP Family_Model: 00100fa0
\r
4 *sysinfo range: [000cc000,000cf360]
\r
6 cpu_init_detectedx = 00000000
\r
7 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000
\r
8 microcode: patch id to apply = 0x010000bf
\r
9 microcode: updated to patch id = 0x010000bf success
\r
17 SB900 - Early.c - get_sbdn - Start.
\r
18 SB900 - Early.c - get_sbdn - End.
\r
19 cpuSetAMDPCI 00 done
\r
20 Prep FID/VID Node:00
\r
21 P-state info in MSRC001_0064 is invalid !!!
\r
22 P-state info in MSRc0010064 is invalid !!!
\r
31 init node: 00 cores: 05
\r
32 Start other core - nodeid: 00 cores: 05
\r
34 started ap apicid: PPPPOPOSOOTSSOSST:TTT::: 0: 000x xxx0x3333300000
\r\r\r\r\r
39 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000035142 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000051324}}}}} ---------------
\r\r\r\r\r
44 * AmmmmmPiiiiiccc cc0rrrrroo1ooocccccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000
\r\r\r\r\r
49 startmemmmmidiiiiccc
\rcc
50 rrrrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff
\r\r\r\r\r
55 mmmm*m iiiiicccAccrrrrrPoo oooccccc0o2oooodddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss
\r\r\r\r\r
65 sccccppctppauuuupSSurSSeeeeStteetttAAAAtdA
\rMMMMDDDM
66 DDMMMMSSMSSRRRRS R * AP 0d odddd3onooonnnene
\reee
\r\r\r
71 stiiiiiannnnniiriiitttttt__e___ffffdfi
\riiiidddd
72 dvvvvviiiiiddddd_____aaaaappppp(((((ssssstttttaaaaagggggeeeee11111))))) aaaaapppppiiiiiccccciiiiiddddd::::: 0000043152
\r\r\r\r\r
77 FFFF*F IIIIIDDDADDPVVVVVII IIIDDDDD0 4 ooooonnnnn AAAAAPPPPP::::: 0000043152
\r\r\r\r\r
87 fam10_optimization()
\r
90 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440
\r
92 FIDVID on BSP, APIC_id: 00
\r
94 Wait for AP stage 1: ap_apicid = 1
\r
96 common_fid(packed) = 0
\r
97 Wait for AP stage 1: ap_apicid = 2
\r
99 common_fid(packed) = 0
\r
100 Wait for AP stage 1: ap_apicid = 3
\r
102 common_fid(packed) = 0
\r
103 Wait for AP stage 1: ap_apicid = 4
\r
105 common_fid(packed) = 0
\r
106 Wait for AP stage 1: ap_apicid = 5
\r
108 common_fid(packed) = 0
\r
111 End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440
\r
112 rs780_htinit cpu_ht_freq=b.
\r
113 rs780_htinit: HT3 mode
\r
119 coreboot-4.0-2002-gee77cf1-dirty Fri Feb 3 02:48:24 CET 2012 starting...
\r
121 BSP Family_Model: 00100fa0
\r
122 *sysinfo range: [000cc000,000cf360]
\r
124 cpu_init_detectedx = 00000000
\r
125 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000
\r
126 microcode: patch id to apply = 0x010000bf
\r
127 microcode: updated to patch id = 0x010000bf success
\r
132 Enter amd_ht_init()
\r
135 SB900 - Early.c - get_sbdn - Start.
\r
136 SB900 - Early.c - get_sbdn - End.
\r
137 cpuSetAMDPCI 00 done
\r
138 Prep FID/VID Node:00
\r
139 P-state info in MSRC001_0064 is invalid !!!
\r
140 P-state info in MSRc0010064 is invalid !!!
\r
148 start_other_cores()
\r
149 init node: 00 cores: 05
\r
150 Start other core - nodeid: 00 cores: 05
\r
152 started ap apicid: PPPPPOOOOOSSSSSTTTTT::::: 00000xxxxx3333300000
\r\r\r\r\r
157 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000041325 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000031245}}}}} ---------------
\r\r\r\r\r
162 * AmmmmmPiiiiiccccc rrrrr0oooo1occcccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000
\r\r\r\r\r
167 startmemmmmiiidiicc
\rcccrr
168 rrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff
\r\r\r\r\r
173 m*mmmm iiiiicccccArrrrProooo occc0ccoo2ooodddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss
\r\r\r\r\r
183 sccppccctupppauuuurSSSSSteeeeettetdAAtt
\rMMAAA
184 DDMMMMMDDDMSSMMSSRRSRRR * AP 0 3dddddooooonnnnneeeee
\r\r\r\r\r
189 stiiiiannnniiiiinrttttit___te_ff_dffif
\riiidi
190 ddddvvvviviiidddid____ds_sssttsttaaaataggggegeeee22222 aa aapppapiiiipciccciiciiddddid:::: : 000 041350
\r2
\r\r\r
199 rs780_early_setup()
\r
200 fam10_optimization()
\r
203 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440
\r
206 End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440
\r
207 rs780_htinit cpu_ht_freq=b.
\r
208 rs780_htinit: HT3 mode
\r
213 raminit_amdmct begin:
\r
214 DIMMPresence: DIMMValid=c
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215 DIMMPresence: DIMMPresent=c
\r
216 DIMMPresence: RegDIMMPresent=0
\r
217 DIMMPresence: DimmECCPresent=0
\r
218 DIMMPresence: DimmPARPresent=0
\r
219 DIMMPresence: Dimmx4Present=0
\r
220 DIMMPresence: Dimmx8Present=c
\r
221 DIMMPresence: Dimmx16Present=0
\r
222 DIMMPresence: DimmPlPresent=0
\r
223 DIMMPresence: DimmDRPresent=c
\r
224 DIMMPresence: DimmQRPresent=0
\r
225 DIMMPresence: DATAload[0]=2
\r
226 DIMMPresence: MAload[0]=10
\r
227 DIMMPresence: MAdimms[0]=1
\r
228 DIMMPresence: DATAload[1]=2
\r
229 DIMMPresence: MAload[1]=10
\r
230 DIMMPresence: MAdimms[1]=1
\r
231 DIMMPresence: Status 1000
\r
232 DIMMPresence: ErrStatus 0
\r
233 DIMMPresence: ErrCode 0
\r
236 DCTInit_D: mct_DIMMPresence Done
\r
237 SPDCalcWidth: Status 1000
\r
238 SPDCalcWidth: ErrStatus 0
\r
239 SPDCalcWidth: ErrCode 0
\r
241 DCTInit_D: mct_SPDCalcWidth Done
\r
242 SPDGetTCL_D: DIMMCASL 4
\r
243 SPDGetTCL_D: DIMMAutoSpeed 4
\r
244 SPDGetTCL_D: Status 1000
\r
245 SPDGetTCL_D: ErrStatus 0
\r
246 SPDGetTCL_D: ErrCode 0
\r
249 AutoCycTiming: Status 1000
\r
250 AutoCycTiming: ErrStatus 0
\r
251 AutoCycTiming: ErrCode 0
\r
252 AutoCycTiming: Done
\r
254 DCTInit_D: AutoCycTiming_D Done
\r
255 SPDSetBanks: CSPresent c
\r
256 SPDSetBanks: Status 1000
\r
257 SPDSetBanks: ErrStatus 0
\r
258 SPDSetBanks: ErrCode 0
\r
261 AfterStitch pDCTstat->NodeSysBase = 0
\r
262 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff
\r
263 StitchMemory: Status 1000
\r
264 StitchMemory: ErrStatus 0
\r
265 StitchMemory: ErrCode 0
\r
268 InterleaveBanks_D: Status 1000
\r
269 InterleaveBanks_D: ErrStatus 0
\r
270 InterleaveBanks_D: ErrCode 0
\r
271 InterleaveBanks_D: Done
\r
273 AutoConfig_D: DramControl: 2a06
\r
274 AutoConfig_D: DramTimingLo: 90092
\r
275 AutoConfig_D: DramConfigMisc: 0
\r
276 AutoConfig_D: DramConfigMisc2: 0
\r
277 AutoConfig_D: DramConfigLo: 10000
\r
278 AutoConfig_D: DramConfigHi: f40000b
\r
279 AutoConfig: Status 1000
\r
280 AutoConfig: ErrStatus 0
\r
281 AutoConfig: ErrCode 0
\r
284 DCTInit_D: AutoConfig_D Done
\r
285 DCTInit_D: PlatformSpec_D Done
\r
286 DCTInit_D: StartupDCT_D
\r
287 DCTInit_D: mct_DIMMPresence Done
\r
288 SPDCalcWidth: Status 1000
\r
289 SPDCalcWidth: ErrStatus 0
\r
290 SPDCalcWidth: ErrCode 0
\r
292 DCTInit_D: mct_SPDCalcWidth Done
\r
293 AutoCycTiming: Status 1000
\r
294 AutoCycTiming: ErrStatus 0
\r
295 AutoCycTiming: ErrCode 0
\r
296 AutoCycTiming: Done
\r
298 DCTInit_D: AutoCycTiming_D Done
\r
299 SPDSetBanks: CSPresent c
\r
300 SPDSetBanks: Status 1000
\r
301 SPDSetBanks: ErrStatus 0
\r
302 SPDSetBanks: ErrCode 0
\r
305 AfterStitch pDCTstat->NodeSysBase = 0
\r
306 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe
\r
307 StitchMemory: Status 1000
\r
308 StitchMemory: ErrStatus 0
\r
309 StitchMemory: ErrCode 0
\r
312 InterleaveBanks_D: Status 1000
\r
313 InterleaveBanks_D: ErrStatus 0
\r
314 InterleaveBanks_D: ErrCode 0
\r
315 InterleaveBanks_D: Done
\r
317 AutoConfig_D: DramControl: 2a06
\r
318 AutoConfig_D: DramTimingLo: 90092
\r
319 AutoConfig_D: DramConfigMisc: 0
\r
320 AutoConfig_D: DramConfigMisc2: 0
\r
321 AutoConfig_D: DramConfigLo: 10000
\r
322 AutoConfig_D: DramConfigHi: f40000b
\r
323 AutoConfig: Status 1000
\r
324 AutoConfig: ErrStatus 0
\r
325 AutoConfig: ErrCode 0
\r
328 DCTInit_D: AutoConfig_D Done
\r
329 DCTInit_D: PlatformSpec_D Done
\r
330 DCTInit_D: StartupDCT_D
\r
331 mctAutoInitMCT_D: SyncDCTsReady_D
\r
332 mctAutoInitMCT_D: HTMemMapInit_D
\r
333 Node: 00 base: 00 limit: 1ffffff BottomIO: c00000
\r
334 Node: 00 base: 03 limit: 23fffff
\r
335 Node: 01 base: 00 limit: 00
\r
336 Node: 02 base: 00 limit: 00
\r
337 Node: 03 base: 00 limit: 00
\r
338 Node: 04 base: 00 limit: 00
\r
339 Node: 05 base: 00 limit: 00
\r
340 Node: 06 base: 00 limit: 00
\r
341 Node: 07 base: 00 limit: 00
\r
342 mctAutoInitMCT_D: CPUMemTyping_D
\r
343 CPUMemTyping: Cache32bTOP:c00000
\r
344 CPUMemTyping: Bottom32bIO:c00000
\r
345 CPUMemTyping: Bottom40bIO:2400000
\r
346 mctAutoInitMCT_D: DQSTiming_D
\r
347 TrainRcvrEn: Status 1100
\r
348 TrainRcvrEn: ErrStatus 0
\r
349 TrainRcvrEn: ErrCode 0
\r
352 TrainDQSRdWrPos: Status 1100
\r
353 TrainDQSRdWrPos: TrainErrors 0
\r
354 TrainDQSRdWrPos: ErrStatus 0
\r
355 TrainDQSRdWrPos: ErrCode 0
\r
356 TrainDQSRdWrPos: Done
\r
358 TrainDQSRdWrPos: Status 1100
\r
359 TrainDQSRdWrPos: TrainErrors 0
\r
360 TrainDQSRdWrPos: ErrStatus 0
\r
361 TrainDQSRdWrPos: ErrCode 0
\r
362 TrainDQSRdWrPos: Done
\r
364 TrainDQSRdWrPos: Status 1100
\r
365 TrainDQSRdWrPos: TrainErrors 0
\r
366 TrainDQSRdWrPos: ErrStatus 0
\r
367 TrainDQSRdWrPos: ErrCode 0
\r
368 TrainDQSRdWrPos: Done
\r
370 TrainDQSRdWrPos: Status 1100
\r
371 TrainDQSRdWrPos: TrainErrors 0
\r
372 TrainDQSRdWrPos: ErrStatus 0
\r
373 TrainDQSRdWrPos: ErrCode 0
\r
374 TrainDQSRdWrPos: Done
\r
376 mctAutoInitMCT_D: UMAMemTyping_D
\r
377 mctAutoInitMCT_D: :OtherTiming
\r
378 InterleaveNodes_D: Status 1100
\r
379 InterleaveNodes_D: ErrStatus 0
\r
380 InterleaveNodes_D: ErrCode 0
\r
381 InterleaveNodes_D: Done
\r
383 InterleaveChannels_D: Node 0
\r
384 InterleaveChannels_D: Status 1100
\r
385 InterleaveChannels_D: ErrStatus 0
\r
386 InterleaveChannels_D: ErrCode 0
\r
387 InterleaveChannels_D: Node 1
\r
388 InterleaveChannels_D: Status 1000
\r
389 InterleaveChannels_D: ErrStatus 0
\r
390 InterleaveChannels_D: ErrCode 0
\r
391 InterleaveChannels_D: Node 2
\r
392 InterleaveChannels_D: Status 1000
\r
393 InterleaveChannels_D: ErrStatus 0
\r
394 InterleaveChannels_D: ErrCode 0
\r
395 InterleaveChannels_D: Node 3
\r
396 InterleaveChannels_D: Status 1000
\r
397 InterleaveChannels_D: ErrStatus 0
\r
398 InterleaveChannels_D: ErrCode 0
\r
399 InterleaveChannels_D: Node 4
\r
400 InterleaveChannels_D: Status 1000
\r
401 InterleaveChannels_D: ErrStatus 0
\r
402 InterleaveChannels_D: ErrCode 0
\r
403 InterleaveChannels_D: Node 5
\r
404 InterleaveChannels_D: Status 1000
\r
405 InterleaveChannels_D: ErrStatus 0
\r
406 InterleaveChannels_D: ErrCode 0
\r
407 InterleaveChannels_D: Node 6
\r
408 InterleaveChannels_D: Status 1000
\r
409 InterleaveChannels_D: ErrStatus 0
\r
410 InterleaveChannels_D: ErrCode 0
\r
411 InterleaveChannels_D: Node 7
\r
412 InterleaveChannels_D: Status 1000
\r
413 InterleaveChannels_D: ErrStatus 0
\r
414 InterleaveChannels_D: ErrCode 0
\r
415 InterleaveChannels_D: Done
\r
417 mctAutoInitMCT_D: ECCInit_D
\r
419 raminit_amdmct end:
\r
424 Copying data from cache to RAM -- switching to use RAM as stack... Done
\r
426 Disabling cache as ram now
\r
427 Clearing initial memory region: Done
\r
429 Searching for fallback/coreboot_ram
\r
430 Check cmos_layout.bin
\r
431 Check fallback/romstage
\r
432 Check fallback/coreboot_ram
\r
433 Stage: loading fallback/coreboot_ram @ 0x200000 (1277952 bytes), entry @ 0x200000
\r
434 Stage: done loading.
\r
438 coreboot-4.0-2002-gee77cf1-dirty Fri Feb 3 02:48:24 CET 2012 booting...
\r
440 Enumerating buses...
\r
441 Show all devs...Before device enumeration.
\r
442 Root Device: enabled 1
\r
443 APIC_CLUSTER: 0: enabled 1
\r
444 APIC: 00: enabled 1
\r
445 PCI_DOMAIN: 0000: enabled 1
\r
446 PCI: 00:18.0: enabled 1
\r
447 PCI: 00:00.0: enabled 1
\r
448 PCI: 00:02.0: enabled 1
\r
449 PCI: 00:03.0: enabled 0
\r
450 PCI: 00:04.0: enabled 1
\r
451 PCI: 00:05.0: enabled 0
\r
452 PCI: 00:06.0: enabled 0
\r
453 PCI: 00:07.0: enabled 0
\r
454 PCI: 00:08.0: enabled 0
\r
455 PCI: 00:09.0: enabled 1
\r
456 PCI: 00:0a.0: enabled 1
\r
457 PCI: 00:11.0: enabled 1
\r
458 PCI: 00:12.0: enabled 1
\r
459 PCI: 00:12.2: enabled 1
\r
460 PCI: 00:13.0: enabled 1
\r
461 PCI: 00:13.2: enabled 1
\r
462 PCI: 00:14.0: enabled 1
\r
463 I2C: 00:50: enabled 1
\r
464 I2C: 00:51: enabled 1
\r
465 I2C: 00:52: enabled 1
\r
466 I2C: 00:53: enabled 1
\r
467 PCI: 00:14.1: enabled 1
\r
468 PCI: 00:14.2: enabled 1
\r
469 PCI: 00:14.3: enabled 1
\r
470 PNP: 002e.0: enabled 0
\r
471 PNP: 002e.1: enabled 0
\r
472 PNP: 002e.2: enabled 1
\r
473 PNP: 002e.3: enabled 1
\r
474 PNP: 002e.5: enabled 1
\r
475 PNP: 002e.6: enabled 0
\r
476 PNP: 002e.7: enabled 0
\r
477 PNP: 002e.8: enabled 0
\r
478 PNP: 002e.9: enabled 0
\r
479 PNP: 002e.a: enabled 0
\r
480 PNP: 002e.b: enabled 1
\r
481 PCI: 00:14.4: enabled 0
\r
482 PCI: 00:14.5: enabled 1
\r
483 PCI: 00:14.6: enabled 0
\r
484 PCI: 00:15.0: enabled 1
\r
485 PCI: 00:15.1: enabled 1
\r
486 PCI: 00:15.2: enabled 1
\r
487 PCI: 00:15.3: enabled 1
\r
488 PCI: 00:16.0: enabled 1
\r
489 PCI: 00:16.2: enabled 1
\r
490 PCI: 00:18.1: enabled 1
\r
491 PCI: 00:18.2: enabled 1
\r
492 PCI: 00:18.3: enabled 1
\r
493 PCI: 00:18.4: enabled 1
\r
494 Compare with tree...
\r
495 Root Device: enabled 1
\r
496 APIC_CLUSTER: 0: enabled 1
\r
497 APIC: 00: enabled 1
\r
498 PCI_DOMAIN: 0000: enabled 1
\r
499 PCI: 00:18.0: enabled 1
\r
500 PCI: 00:00.0: enabled 1
\r
501 PCI: 00:02.0: enabled 1
\r
502 PCI: 00:03.0: enabled 0
\r
503 PCI: 00:04.0: enabled 1
\r
504 PCI: 00:05.0: enabled 0
\r
505 PCI: 00:06.0: enabled 0
\r
506 PCI: 00:07.0: enabled 0
\r
507 PCI: 00:08.0: enabled 0
\r
508 PCI: 00:09.0: enabled 1
\r
509 PCI: 00:0a.0: enabled 1
\r
510 PCI: 00:11.0: enabled 1
\r
511 PCI: 00:12.0: enabled 1
\r
512 PCI: 00:12.2: enabled 1
\r
513 PCI: 00:13.0: enabled 1
\r
514 PCI: 00:13.2: enabled 1
\r
515 PCI: 00:14.0: enabled 1
\r
516 I2C: 00:50: enabled 1
\r
517 I2C: 00:51: enabled 1
\r
518 I2C: 00:52: enabled 1
\r
519 I2C: 00:53: enabled 1
\r
520 PCI: 00:14.1: enabled 1
\r
521 PCI: 00:14.2: enabled 1
\r
522 PCI: 00:14.3: enabled 1
\r
523 PNP: 002e.0: enabled 0
\r
524 PNP: 002e.1: enabled 0
\r
525 PNP: 002e.2: enabled 1
\r
526 PNP: 002e.3: enabled 1
\r
527 PNP: 002e.5: enabled 1
\r
528 PNP: 002e.6: enabled 0
\r
529 PNP: 002e.7: enabled 0
\r
530 PNP: 002e.8: enabled 0
\r
531 PNP: 002e.9: enabled 0
\r
532 PNP: 002e.a: enabled 0
\r
533 PNP: 002e.b: enabled 1
\r
534 PCI: 00:14.4: enabled 0
\r
535 PCI: 00:14.5: enabled 1
\r
536 PCI: 00:14.6: enabled 0
\r
537 PCI: 00:15.0: enabled 1
\r
538 PCI: 00:15.1: enabled 1
\r
539 PCI: 00:15.2: enabled 1
\r
540 PCI: 00:15.3: enabled 1
\r
541 PCI: 00:16.0: enabled 1
\r
542 PCI: 00:16.2: enabled 1
\r
543 PCI: 00:18.1: enabled 1
\r
544 PCI: 00:18.2: enabled 1
\r
545 PCI: 00:18.3: enabled 1
\r
546 PCI: 00:18.4: enabled 1
\r
547 Mainboard ASUS M5A99X-EVO Enable. dev=0x00232810
\r
548 m5a99x_evo_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
\r
549 m5a99x_evo_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000002
\r
550 m5a99x_evo_enable: uma size 0x10000000, memory start 0xb0000000
\r
551 m5a99x_evo_enable, w00t?!
\r
552 m5a99x_evo_enable, cya enable?!
\r
553 scan_static_bus for Root Device
\r
554 APIC_CLUSTER: 0 enabled
\r
555 PCI_DOMAIN: 0000 enabled
\r
556 APIC_CLUSTER: 0 scanning...
\r
557 PCI: 00:18.3 siblings=5
\r
558 CPU: APIC: 00 enabled
\r
559 CPU: APIC: 01 enabled
\r
560 CPU: APIC: 02 enabled
\r
561 CPU: APIC: 03 enabled
\r
562 CPU: APIC: 04 enabled
\r
563 CPU: APIC: 05 enabled
\r
564 PCI_DOMAIN: 0000 scanning...
\r
565 PCI: pci_scan_bus for bus 00
\r
567 PCI: 00:18.0 [1022/1200] bus ops
\r
568 PCI: 00:18.0 [1022/1200] enabled
\r
569 PCI: 00:18.1 [1022/1201] enabled
\r
570 PCI: 00:18.2 [1022/1202] enabled
\r
571 PCI: 00:18.3 [1022/1203] ops
\r
572 PCI: 00:18.3 [1022/1203] enabled
\r
573 PCI: 00:18.4 [1022/1204] enabled
\r
575 PCI: Using configuration type 1
\r
576 rs780_enable: dev=00232ddc, VID_DID=0x5a141002
\r
577 Bus-0, Dev-0, Fun-0.
\r
579 addr=e0000000,bus=0,devfn=40
\r
580 gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
\r
582 NB_PCI_REG84 = 3000095.
\r
583 NB_PCI_REG4C = 52042.
\r
585 PCI: 00:00.0 [1002/5a14] enabled
\r
586 Capability: type 0x08 @ 0xf0
\r
588 Capability: type 0x08 @ 0xf0
\r
589 Capability: type 0x08 @ 0xc4
\r
591 PCI: pci_scan_bus for bus 00
\r
592 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff
\r
593 PCI: pci_scan_bus upper limit too big. Using 0xff.
\r
595 rs780_enable: dev=00232ddc, VID_DID=0x5a141002
\r
596 Bus-0, Dev-0, Fun-0.
\r
598 gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
\r
600 NB_PCI_REG84 = 3000095.
\r
601 NB_PCI_REG4C = 52042.
\r
603 PCI: 00:00.0 [1002/5a14] enabled
\r