inserting a dummy state
[hwmod.git] / src / history.vhd
index 46acf193288268c2fb6b36be910bbf7cce3921ee..ddd26f62b11fbc4233c8700c442cac2419d78c79 100644 (file)
@@ -42,7 +42,7 @@ end entity history;
 architecture beh of history is
        type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
                S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE,
-               S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_READ);
+               S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_DUMMY ,S_PC_READ);
        signal state_int, state_next : HISTORY_STATE;
        signal was_bs_int, was_bs_next : std_logic;
        signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
@@ -201,9 +201,11 @@ begin
                                        state_next <= SIDLE;
                                end if;
                        when S_PC_INIT =>
+                               state_next <= S_PC_DUMMY;
+                       when S_PC_DUMMY =>
                                state_next <= S_PC_READ;
                        when S_PC_READ =>
-                               if d_get = '0' then
+                               if pc_get = '0' then
                                        state_next <= SIDLE;
                                end if;
                        when S_P_READ =>
@@ -245,7 +247,7 @@ begin
                address_next <= address_int;
                data_in_next <= data_in_int;
                pc_done_next <= '0';
-               pc_char_next <= pc_char_int; --(others => '0');
+               pc_char_next <= pc_char_int;
                pc_busy_next <= '0';
                p_rdone_next <= p_rdone_int;
                p_wdone_next <= p_wdone_int;
@@ -356,6 +358,8 @@ begin
                                addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte));
                                address_next <= addr_tmp;
                                pc_busy_next <= '1';
+                       when S_PC_DUMMY =>
+                               pc_busy_next <= '1';
                        when S_PC_READ =>
                                pc_char_next <= data_out;
                                pc_done_next <= '1';