pc_com: p_busy ist unnoetig und noch ein paar kleinere fehler ausgebessert

[hwmod.git] / src / beh_history_tb.vhd

diff --git a/src/beh_history_tb.vhd b/src/beh_history_tb.vhd
index d05236adfb851ffea9e8a69b8c1b52fea164301f..87115c724c2ed37b7ed3faa0634838bea4ee4250 100644 (file)
--- a/src/beh_history_tb.vhd
+++ b/src/beh_history_tb.vhd
@@ -46,13 +46,9 @@ architecture sim of beh_history_tb is
        signal pc_spalte : hspalte;
        signal pc_get, pc_done : std_logic;
        signal pc_char : hbyte;
-       signal pc_busy : std_logic;
        --dummy button
        signal btn_a_int : std_logic;
 
-       --output beautifier
-       signal tx_debug : character;
-
        signal stop : boolean := false;
 begin
        -- history
@@ -87,7 +83,6 @@ begin
                pc_spalte => pc_spalte,
                pc_zeile  => pc_zeile,
                pc_char   => pc_char,
-               pc_busy   => pc_busy,
                pc_done   => pc_done
        );
 
@@ -176,10 +171,8 @@ begin
                pc_spalte => pc_spalte,
                pc_get    => pc_get,
                pc_done   => pc_done,
-               pc_char   => pc_char,
-               pc_busy   => pc_busy
+               pc_char   => pc_char
        );
-       tx_debug <= character'val(to_integer(unsigned(tx_data)));
 
        process
        begin
@@ -310,7 +303,8 @@ begin
                        report "==================";
                end loop f_loop;
 
-               icwait(sys_clk, 850);
+               -- uart ist ziemlich langsam...
+               icwait(sys_clk, 1000000000);
                stop <= true;
                wait;
        end process;
@@ -319,7 +313,7 @@ begin
        begin
                btn_a_int <= '1';
                wait until sys_res_n = '1';
-               wait for 50000 * 15 ns;
+               icwait(sys_clk, 50000);
                wait until rising_edge(sys_clk);
                btn_a_int <= '0';
                wait for 30 ns;