--- /dev/null
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+ if {[string compare $quartus(project) "calc"]} {
+ puts "Project calc is not open"
+ set make_assignments 0
+ }
+} else {
+ # Only open if not already open
+ if {[project_exists calc]} {
+ project_open -revision calc calc
+ } else {
+ project_new -revision calc calc
+ }
+ set need_to_close_project 1
+}
+
+# Make assignments
+if {$make_assignments} {
+ set_global_assignment -name FAMILY Stratix
+ set_global_assignment -name DEVICE %DEVICE%
+ set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
+ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+ set_global_assignment -name MISC_FILE "calc.dpf"
+ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+ set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+ set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+
+ set_global_assignment -name TOP_LEVEL_ENTITY alu
+ set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../../src/alu.vhd
+
+ #pin mapping/system
+ set_location_assignment PIN_N3 -to sys_clk
+ set_location_assignment PIN_AF17 -to sys_res_n
+
+ # Commit assignments
+ export_assignments
+
+ # Close project
+ if {$need_to_close_project} {
+ project_close
+ }
+}