--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+architecture beh of sync is\r
+ signal sync : std_logic_vector(1 to SYNC_STAGES);\r
+begin\r
+ process(sys_clk, sys_res_n)\r
+ begin\r
+ if sys_res_n = '0' then\r
+ sync <= (others => RESET_VALUE);\r
+ elsif rising_edge(sys_clk) then\r
+ sync(1) <= data_in;\r
+ for i in 2 to SYNC_STAGES loop\r
+ sync(i) <= sync(i - 1);\r
+ end loop;\r
+ end if;\r
+ end process;\r
+ data_out <= sync(SYNC_STAGES);\r
+end architecture beh;\r