after slot5

[dide_16.git] / bsp4 / Designflow / syn / rev_1 / vga_rm.tcl

diff --git a/bsp4/Designflow/syn/rev_1/vga_rm.tcl b/bsp4/Designflow/syn/rev_1/vga_rm.tcl
new file mode 100644 (file)
index 0000000..b20c77f
--- /dev/null
+++ b/bsp4/Designflow/syn/rev_1/vga_rm.tcl
@@ -0,0 +1,12 @@
+set_global_assignment -name TOP_LEVEL_ENTITY "|vga" -remove 
+set_global_assignment -name FAMILY -remove 
+set_global_assignment -name TAO_FILE "myresults.tao" -remove
+set_global_assignment -name SOURCES_PER_DESTINATION_INCLUDE_COUNT "1000" -remove 
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON -remove 
+set_global_assignment -name REMOVE_DUPLICATE_LOGIC "OFF" -remove 
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS "OFF" -remove 
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS "OFF" -remove 
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS "OFF" -remove 
+set_global_assignment -name REMOVE_DUPLICATE_LOGIC "OFF" -remove 
+#set_global_assignment -name EDA_RESYNTHESIS_TOOL "AMPLIFY" -remove
+create_base_clock clk_pin_setting -fmax 25.175mhz -duty_cycle 50.00 -target clk_pin -disable