after slot5

[dide_16.git] / bsp4 / Designflow / syn / rev_1 / vga.tcl

diff --git a/bsp4/Designflow/syn/rev_1/vga.tcl b/bsp4/Designflow/syn/rev_1/vga.tcl
new file mode 100644 (file)
index 0000000..65e3b45
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+++ b/bsp4/Designflow/syn/rev_1/vga.tcl
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+# Run with quartus_sh -t <x_cons.tcl>
+
+# Global assignments 
+set_global_assignment -name TOP_LEVEL_ENTITY "|vga"
+set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE NORMAL
+set_global_assignment -name FAMILY "STRATIX"
+set_global_assignment -name DEVICE "EP1S25F672C6"
+set_global_assignment -section_id vga -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "SYNPLIFY"
+set_global_assignment -section_id eda_design_synthesis -name EDA_USE_LMF synplcty.lmf
+set_global_assignment -name TAO_FILE "myresults.tao"
+set_global_assignment -name SOURCES_PER_DESTINATION_INCLUDE_COUNT "1000" 
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS "OFF"
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS "OFF"
+set_global_assignment -name REMOVE_DUPLICATE_LOGIC "OFF"
+# set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+#set_global_assignment -name EDA_RESYNTHESIS_TOOL "AMPLIFY"
+set_global_assignment -name ENABLE_CLOCK_LATENCY "ON"
+
+# Clock assignments 
+
+create_base_clock clk_pin_setting -fmax 25.175mhz -duty_cycle 50.00 -target clk_pin 
+
+
+# False path constraints 
+
+# Multicycle constraints 
+
+# Path delay constraints 
+if {[file exists ___quartus_options.tcl]} {
+       source ___quartus_options.tcl
+}
+
+
+# Incremental Compilation
+    # this will synchronize any existing partitions declared in Synpilfy
+    # with partitions existing in Quartus. If partitions exist,
+    # incremental compilation will be enabled
+    variable compile_point_list
+    set compile_point_list [list]
+    source "/opt/synplify/fpga_c200906/lib/altera/qic.tcl"