--- /dev/null
+#Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
+#install: /opt/synplify/fpga_c200906
+#OS: Linux
+#Hostname: ti14
+
+#Implementation: rev_1
+
+#Tue Nov 3 17:21:38 2009
+
+$ Start of Compile
+#Tue Nov 3 17:21:38 2009
+
+Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
+Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved
+
+@N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
+@N:"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_ent.vhd":38:7:38:9|Top entity is set to vga.
+VHDL syntax check successful!
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_ent.vhd":38:7:38:9|Synthesizing work.vga.behav
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_control_ent.vhd":37:7:37:17|Synthesizing work.vga_control.behav
+Post processing for work.vga_control.behav
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_driver_ent.vhd":37:7:37:16|Synthesizing work.vga_driver.behav
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
+Post processing for work.vga_driver.behav
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/board_driver_ent.vhd":36:7:36:18|Synthesizing work.board_driver.behav
+Post processing for work.board_driver.behav
+Post processing for work.vga.behav
+@END
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Nov 3 17:21:39 2009
+
+###########################################################]
+Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53
+Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved
+Product Version C-2009.06
+@N: MF249 |Running in 32-bit mode.
+@N: MF257 |Gated clock conversion enabled
+@N|Running in logic synthesis mode without enhanced optimization
+
+Automatic dissolve during optimization of view:work.vga(behav) of board_driver_unit(board_driver)
+Automatic dissolve at startup in view:work.vga(behav) of vga_control_unit(vga_control)
+
+Available hyper_sources - for debug and ip models
+ None Found
+
+Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+@N:"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_driver_arc.vhd":267:4:267:5|Found counter in view:work.vga_driver(behav) inst vsync_counter[9:0]
+@N:"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_driver_arc.vhd":158:4:158:5|Found counter in view:work.vga_driver(behav) inst hsync_counter[9:0]
+Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
+
+
+
+#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[
+
+======================================================================================
+ Instance:Pin Generated Clock Optimization Status
+======================================================================================
+
+
+##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]
+
+Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished technology mapping (Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 67MB)
+
+Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
+
+Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 69MB)
+
+
+Writing Analyst data base /homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.srm
+Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
+
+Writing Verilog Netlist and constraint files
+Writing .vqm output for Quartus
+Writing Cross reference file for Quartus to /homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.xrf
+Finished Writing Verilog Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
+
+Writing VHDL Simulation files
+Finished Writing VHDL Simulation files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
+
+Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
+
+@N: MF276 |Gated clock conversion enabled, but no gated clocks found in design
+Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
+
+Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
+
+@N: MF333 |Generated clock conversion enabled, but no generated clocks found in design
+Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
+
+Found clock vga|clk_pin with period 39.72ns
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Tue Nov 3 17:21:46 2009
+#
+
+
+Top view: vga
+Requested Frequency: 25.2 MHz
+Wire load mode: top
+Paths requested: 5
+Constraint File(s):
+@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
+
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 34.465
+
+ Requested Estimated Requested Estimated Clock Clock
+Starting Clock Frequency Frequency Period Period Slack Type Group
+----------------------------------------------------------------------------------------------------------------------
+vga|clk_pin 25.2 MHz 190.2 MHz 39.722 5.257 34.465 inferred Inferred_clkgroup_0
+======================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks | rise to rise | fall to fall | rise to fall | fall to rise
+-----------------------------------------------------------------------------------------------------------------
+Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
+-----------------------------------------------------------------------------------------------------------------
+vga|clk_pin vga|clk_pin | 39.722 34.465 | No paths - | No paths - | No paths -
+=================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+ 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information
+*********************
+
+ No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: vga|clk_pin
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+--------------------------------------------------------------------------------------------------------------------------------------
+dly_counter[0] vga|clk_pin stratix_lcell_ff regout dly_counter[0] 0.176 34.465
+dly_counter[1] vga|clk_pin stratix_lcell_ff regout dly_counter[1] 0.176 34.584
+vga_driver_unit.vsync_counter[6] vga|clk_pin stratix_lcell_ff regout vsync_counter_6 0.176 34.836
+vga_driver_unit.vsync_counter[7] vga|clk_pin stratix_lcell_ff regout vsync_counter_7 0.176 34.865
+vga_control_unit.toggle_counter_sig[1] vga|clk_pin stratix_lcell_ff regout toggle_counter_sig_1 0.176 34.968
+vga_driver_unit.vsync_counter[3] vga|clk_pin stratix_lcell_ff regout vsync_counter_3 0.176 34.992
+vga_driver_unit.vsync_counter[8] vga|clk_pin stratix_lcell_ff regout vsync_counter_8 0.176 34.992
+vga_control_unit.toggle_counter_sig[5] vga|clk_pin stratix_lcell_ff regout toggle_counter_sig_5 0.176 35.095
+vga_driver_unit.vsync_counter[5] vga|clk_pin stratix_lcell_ff regout vsync_counter_5 0.176 35.111
+vga_driver_unit.vsync_counter[4] vga|clk_pin stratix_lcell_ff regout vsync_counter_4 0.176 35.119
+======================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+-----------------------------------------------------------------------------------------------------------------------------------
+vga_driver_unit.vsync_state[2] vga|clk_pin stratix_lcell_ff ena vsync_state_next_2_sqmuxa 38.986 34.465
+vga_driver_unit.vsync_state[3] vga|clk_pin stratix_lcell_ff ena vsync_state_next_2_sqmuxa 38.986 34.465
+vga_driver_unit.vsync_state[4] vga|clk_pin stratix_lcell_ff ena vsync_state_next_2_sqmuxa 38.986 34.465
+vga_driver_unit.vsync_state[5] vga|clk_pin stratix_lcell_ff ena vsync_state_next_2_sqmuxa 38.986 34.465
+vga_driver_unit.vsync_state[6] vga|clk_pin stratix_lcell_ff datab dly_counter_0 35.641 34.465
+vga_driver_unit.vsync_state[6] vga|clk_pin stratix_lcell_ff datac dly_counter_1 35.760 34.584
+vga_driver_unit.hsync_state[0] vga|clk_pin stratix_lcell_ff ena hsync_state_3_0_0_0__g0_0 38.986 34.711
+vga_driver_unit.hsync_state[1] vga|clk_pin stratix_lcell_ff ena hsync_state_3_0_0_0__g0_0 38.986 34.711
+vga_driver_unit.hsync_state[2] vga|clk_pin stratix_lcell_ff ena hsync_state_3_0_0_0__g0_0 38.986 34.711
+vga_driver_unit.hsync_state[3] vga|clk_pin stratix_lcell_ff ena hsync_state_3_0_0_0__g0_0 38.986 34.711
+===================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 39.722
+ - Setup time: 0.736
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 38.986
+
+ - Propagation time: 4.521
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (critical) : 34.465
+
+ Number of logic level(s): 2
+ Starting point: dly_counter[0] / regout
+ Ending point: vga_driver_unit.vsync_state[2] / ena
+ The start point is clocked by vga|clk_pin [rising] on pin clk
+ The end point is clocked by vga|clk_pin [rising] on pin clk
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------
+dly_counter[0] stratix_lcell_ff regout Out 0.176 0.176 -
+dly_counter[0] Net - - 1.000 - 9
+vga_driver_unit.vsync_state[6] stratix_lcell_ff datab In - 1.176 -
+vga_driver_unit.vsync_state[6] stratix_lcell_ff combout Out 0.332 1.508 -
+un6_dly_counter_0_x Net - - 2.160 - 58(49)
+vga_driver_unit.vsync_state_next_2_sqmuxa stratix_lcell dataa In - 3.668 -
+vga_driver_unit.vsync_state_next_2_sqmuxa stratix_lcell combout Out 0.459 4.127 -
+vsync_state_next_2_sqmuxa Net - - 0.393 - 5(2)
+vga_driver_unit.vsync_state[2] stratix_lcell_ff ena In - 4.521 -
+=======================================================================================================================
+Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 5.257 is 1.703(32.4%) logic and 3.554(67.6%) route.
+Fanout format: logic fanout (physical fanout)
+Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
+*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
+
+
+
+##### END OF TIMING REPORT #####]
+
+##### START OF AREA REPORT #####[
+Design view:work.vga(behav)
+Selecting part EP1S25F672C6
+@N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
+
+I/O ATOMs: 117
+
+Total LUTs: 181 of 25660 ( 0%)
+Logic resources: 183 ATOMs of 25660 ( 0%)
+
+Number of I/O registers
+ Output DDRs :0
+
+ATOM count by mode:
+ normal: 131
+ arithmetic: 52
+
+DSP Blocks: 0 (0 nine-bit DSP elements).
+DSP Utilization: 0.00% of available 10 blocks (80 nine-bit).
+ShiftTap: 0 (0 registers)
+MRAM: 0 (0% of 2)
+M4Ks: 0 (0% of 138)
+M512s: 0 (0% of 224)
+Total ESB: 0 bits
+
+ATOMs using regout pin: 88
+ also using enable pin: 12
+ also using combout pin: 1
+ATOMs using combout pin: 93
+Number of Inputs on ATOMs: 759
+Number of Nets: 55530
+
+##### END OF AREA REPORT #####]
+
+Mapper successful!
+Process took 0h:00m:05s realtime, 0h:00m:04s cputime
+# Tue Nov 3 17:21:46 2009
+
+###########################################################]
projects / dide_16.git / blobdiff