after slot5

[dide_16.git] / bsp4 / Designflow / syn / rev_1 / syntmp / vga_cons_ui.tcl

diff --git a/bsp4/Designflow/syn/rev_1/syntmp/vga_cons_ui.tcl b/bsp4/Designflow/syn/rev_1/syntmp/vga_cons_ui.tcl
new file mode 100644 (file)
index 0000000..c791b24
--- /dev/null
+++ b/bsp4/Designflow/syn/rev_1/syntmp/vga_cons_ui.tcl
@@ -0,0 +1,5 @@
+source "/opt/synplify/fpga_c200906/lib/altera/quartus_cons.tcl"
+syn_create_and_open_prj vga
+source $::quartus(binpath)/prj_asd_import.tcl
+syn_create_and_open_csf vga
+syn_handle_cons vga