--- /dev/null
+-- megafunction wizard: %ALTPLL%\r
+-- GENERATION: STANDARD\r
+-- VERSION: WM1.0\r
+-- MODULE: altpll \r
+\r
+-- ============================================================\r
+-- File Name: vpll.vhd\r
+-- Megafunction Name(s):\r
+-- altpll\r
+-- ============================================================\r
+-- ************************************************************\r
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+--\r
+-- 4.1 Build 181 06/29/2004 SJ Full Version\r
+-- ************************************************************\r
+\r
+\r
+--Copyright (C) 1991-2004 Altera Corporation\r
+--Any megafunction design, and related netlist (encrypted or decrypted),\r
+--support information, device programming or simulation file, and any other\r
+--associated documentation or information provided by Altera or a partner\r
+--under Altera's Megafunction Partnership Program may be used only\r
+--to program PLD devices (but not masked PLD devices) from Altera. Any\r
+--other use of such megafunction design, netlist, support information,\r
+--device programming or simulation file, or any other related documentation\r
+--or information is prohibited for any other purpose, including, but not\r
+--limited to modification, reverse engineering, de-compiling, or use with\r
+--any other silicon devices, unless such use is explicitly licensed under\r
+--a separate agreement with Altera or a megafunction partner. Title to the\r
+--intellectual property, including patents, copyrights, trademarks, trade\r
+--secrets, or maskworks, embodied in any such megafunction design, netlist,\r
+--support information, device programming or simulation file, or any other\r
+--related documentation or information provided by Altera or a megafunction\r
+--partner, remains with Altera, the megafunction partner, or their respective\r
+--licensors. No other licenses, including any licenses needed under any third\r
+--party's intellectual property, are provided herein.\r
+\r
+\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.all;\r
+\r
+LIBRARY altera_mf;\r
+USE altera_mf.altera_mf_components.all;\r
+\r
+ENTITY vpll IS\r
+ PORT\r
+ (\r
+ inclk0 : IN STD_LOGIC := '0';\r
+-- pllena : IN STD_LOGIC := '1';\r
+-- areset : IN STD_LOGIC := '0';\r
+ c0 : OUT STD_LOGIC \r
+-- locked : OUT STD_LOGIC \r
+ );\r
+END vpll;\r
+\r
+\r
+ARCHITECTURE SYN OF vpll IS\r
+\r
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);\r
+ SIGNAL sub_wire1 : STD_LOGIC ;\r
+ SIGNAL sub_wire2 : STD_LOGIC ;\r
+ SIGNAL sub_wire3_bv : BIT_VECTOR (0 DOWNTO 0);\r
+ SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);\r
+ SIGNAL sub_wire4 : STD_LOGIC_VECTOR (5 DOWNTO 0);\r
+ SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);\r
+ SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);\r
+ SIGNAL sub_wire6 : STD_LOGIC ;\r
+ SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);\r
+ SIGNAL sub_wire8 : STD_LOGIC_VECTOR (3 DOWNTO 0);\r
+\r
+signal pllena_int : std_logic;\r
+signal areset_int : std_logic;\r
+signal locked : std_logic;\r
+\r
+ COMPONENT altpll\r
+ GENERIC (\r
+ bandwidth_type : STRING;\r
+ clk0_duty_cycle : NATURAL;\r
+ lpm_type : STRING;\r
+ clk0_multiply_by : NATURAL;\r
+ invalid_lock_multiplier : NATURAL;\r
+ inclk0_input_frequency : NATURAL;\r
+ gate_lock_signal : STRING;\r
+ clk0_divide_by : NATURAL;\r
+ pll_type : STRING;\r
+ valid_lock_multiplier : NATURAL;\r
+ clk0_time_delay : STRING;\r
+ spread_frequency : NATURAL;\r
+ intended_device_family : STRING;\r
+ operation_mode : STRING;\r
+ compensate_clock : STRING;\r
+ clk0_phase_shift : STRING\r
+ );\r
+ PORT (\r
+ clkena : IN STD_LOGIC_VECTOR (5 DOWNTO 0);\r
+ inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);\r
+ pllena : IN STD_LOGIC ;\r
+ extclkena : IN STD_LOGIC_VECTOR (3 DOWNTO 0);\r
+ locked : OUT STD_LOGIC ;\r
+ areset : IN STD_LOGIC ;\r
+ clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+BEGIN\r
+ sub_wire3_bv(0 DOWNTO 0) <= "0";\r
+ sub_wire3 <= To_stdlogicvector(sub_wire3_bv);\r
+ sub_wire5_bv(0 DOWNTO 0) <= "0";\r
+ sub_wire5 <= NOT(To_stdlogicvector(sub_wire5_bv));\r
+ sub_wire1 <= sub_wire0(0);\r
+ c0 <= sub_wire1;\r
+ locked <= sub_wire2;\r
+ sub_wire4 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire5(0 DOWNTO 0);\r
+ sub_wire6 <= inclk0;\r
+ sub_wire7 <= sub_wire3(0 DOWNTO 0) & sub_wire6;\r
+ sub_wire8 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0);\r
+\r
+areset_int <= '0';\r
+pllena_int <= '1';\r
+\r
+ altpll_component : altpll\r
+ GENERIC MAP (\r
+ bandwidth_type => "AUTO",\r
+ clk0_duty_cycle => 50,\r
+ lpm_type => "altpll",\r
+ clk0_multiply_by => 5435,\r
+ invalid_lock_multiplier => 5,\r
+ inclk0_input_frequency => 30003,\r
+ gate_lock_signal => "NO",\r
+ clk0_divide_by => 6666,\r
+ pll_type => "AUTO",\r
+ valid_lock_multiplier => 1,\r
+ clk0_time_delay => "0",\r
+ spread_frequency => 0,\r
+ intended_device_family => "Stratix",\r
+ operation_mode => "NORMAL",\r
+ compensate_clock => "CLK0",\r
+ clk0_phase_shift => "0"\r
+ )\r
+ PORT MAP (\r
+ clkena => sub_wire4,\r
+ inclk => sub_wire7,\r
+ pllena => pllena_int,\r
+ extclkena => sub_wire8,\r
+ areset => areset_int,\r
+ clk => sub_wire0,\r
+ locked => sub_wire2\r
+ );\r
+\r
+\r
+\r
+END SYN;\r
+\r
+-- ============================================================\r
+-- CNX file retrieval info\r
+-- ============================================================\r
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"\r
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"\r
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"\r
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"\r
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"\r
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"\r
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"\r
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"\r
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"\r
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"\r
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"\r
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"\r
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"\r
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"\r
+-- Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"\r
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"\r
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"\r
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"\r
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"\r
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"\r
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"\r
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"\r
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"\r
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "33.330"\r
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"\r
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"\r
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"\r
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"\r
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"\r
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"\r
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"\r
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"\r
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"\r
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"\r
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"\r
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "299.970"\r
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"\r
+-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1"\r
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.330"\r
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"\r
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "27.175"\r
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"\r
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix"\r
+-- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"\r
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"\r
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"\r
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"\r
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"\r
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"\r
+-- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "9"\r
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"\r
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"\r
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"\r
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5435"\r
+-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"\r
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30003"\r
+-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"\r
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6666"\r
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"\r
+-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"\r
+-- Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"\r
+-- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"\r
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"\r
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"\r
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"\r
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"\r
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"\r
+-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"\r
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"\r
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"\r
+-- Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena"\r
+-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"\r
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]"\r
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"\r
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0\r
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0\r
+-- Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0\r
+-- Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0\r
+-- Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0\r
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.vhd TRUE FALSE\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.inc FALSE FALSE\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.cmp TRUE FALSE\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.bsf TRUE\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd TRUE FALSE\r
projects / dide_16.git / blobdiff