after slot5

[dide_16.git] / bsp4 / Designflow / src / vpll.bsf

diff --git a/bsp4/Designflow/src/vpll.bsf b/bsp4/Designflow/src/vpll.bsf
new file mode 100644 (file)
index 0000000..63c3118
--- /dev/null
+++ b/bsp4/Designflow/src/vpll.bsf
@@ -0,0 +1,49 @@
+/*\r
+WARNING: Do NOT edit the input and output ports in this file in a text\r
+editor if you plan to continue editing the block that represents it in\r
+the Block Editor! File corruption is VERY likely to occur.\r
+*/\r
+/*\r
+Copyright (C) 1991-2004 Altera Corporation\r
+Any  megafunction  design,  and related netlist (encrypted  or  decrypted),\r
+support information,  device programming or simulation file,  and any other\r
+associated  documentation or information  provided by  Altera  or a partner\r
+under  Altera's   Megafunction   Partnership   Program  may  be  used  only\r
+to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any\r
+other  use  of such  megafunction  design,  netlist,  support  information,\r
+device programming or simulation file,  or any other  related documentation\r
+or information  is prohibited  for  any  other purpose,  including, but not\r
+limited to  modification,  reverse engineering,  de-compiling, or use  with\r
+any other  silicon devices,  unless such use is  explicitly  licensed under\r
+a separate agreement with  Altera  or a megafunction partner.  Title to the\r
+intellectual property,  including patents,  copyrights,  trademarks,  trade\r
+secrets,  or maskworks,  embodied in any such megafunction design, netlist,\r
+support  information,  device programming or simulation file,  or any other\r
+related documentation or information provided by  Altera  or a megafunction\r
+partner, remains with Altera, the megafunction partner, or their respective\r
+licensors. No other licenses, including any licenses needed under any third\r
+party's intellectual property, are provided herein.\r
+*/\r
+(header "symbol" (version "1.1"))\r
+(symbol\r
+       (rect 16 16 112 112)\r
+       (text "vpll" (rect 5 0 22 12)(font "Arial" ))\r
+       (text "inst" (rect 8 80 25 92)(font "Arial" ))\r
+       (port\r
+               (pt 0 32)\r
+               (input)\r
+               (text "inclk0" (rect 0 0 28 12)(font "Arial" ))\r
+               (text "inclk0" (rect 21 27 49 39)(font "Arial" ))\r
+               (line (pt 0 32)(pt 16 32)(line_width 1))\r
+       )\r
+       (port\r
+               (pt 96 32)\r
+               (output)\r
+               (text "c0" (rect 0 0 11 12)(font "Arial" ))\r
+               (text "c0" (rect 64 27 75 39)(font "Arial" ))\r
+               (line (pt 96 32)(pt 80 32)(line_width 1))\r
+       )\r
+       (drawing\r
+               (rectangle (rect 16 16 80 80)(line_width 1))\r
+       )\r
+)\r