after slot5

[dide_16.git] / bsp4 / Designflow / src / vga_pak.vhd

diff --git a/bsp4/Designflow/src/vga_pak.vhd b/bsp4/Designflow/src/vga_pak.vhd
new file mode 100644 (file)
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+++ b/bsp4/Designflow/src/vga_pak.vhd
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+-------------------------------------------------------------------------------\r
+-- Title      : vga package\r
+-- Project    : LU Digital Design\r
+-------------------------------------------------------------------------------\r
+-- File       : vga_pak.vhd\r
+-- Author     : Thomas Handl\r
+-- Company    : TU Wien\r
+-- Created    : 2004-08-19\r
+-- Last update: 2006-02-24\r
+-------------------------------------------------------------------------------\r
+-- Description: definitions of global constants and enumerated types\r
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2004 TU Wien\r
+-------------------------------------------------------------------------------\r
+-- Revisions  :\r
+-- Date        Version  Author  Description\r
+-- 2004-08-19  1.0      handl   Created\r
+-- 2006-02-24  2.0      ST      revised\r
+-------------------------------------------------------------------------------\r
+\r
+-------------------------------------------------------------------------------\r
+-- LIBRARIES\r
+-------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.std_logic_unsigned.all;\r
+use IEEE.std_logic_arith.all;\r
+\r
+\r
+-------------------------------------------------------------------------------\r
+-- PACKAGE\r
+-------------------------------------------------------------------------------\r
+\r
+package vga_pak is\r
+\r
+  constant RES_ACT   : std_logic := '0';            -- define reset active LO\r
+  constant ENABLE    : std_logic := '1';            -- define diverse enable HI\r
+  constant COLR_ON    : std_logic := '1';           -- define VGA color on as HI\r
+  constant COLR_OFF   : std_logic := '0';           -- define VGA color off as LO\r
+  constant SEG_WIDTH : integer := 7;                -- display has 7 segments\r
+  constant BCD_WIDTH : integer := 4;                -- BCD number has 4 bit\r
+  constant TOG_CNT_WIDTH : integer := 25;           -- bitwidth of counter that controls blinking\r
+\r
+  constant COL_CNT_WIDTH   : integer := 10;          -- width of the column counter\r
+  constant LINE_CNT_WIDTH  : integer := 9;           -- width of the line counter\r
+  constant HSYN_CNT_WIDTH : integer := 10;          -- width of the h-sync counter\r
+  constant VSYN_CNT_WIDTH : integer := 10;          -- width of the v-sync counter\r
+\r
+  constant RIGHT_BORDER:  std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "1001111111";  -- 640 columns (0...639)\r
+  constant BOTTOM_BORDER: std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "111011111";   -- 480 lines (0...479)\r
+\r
+  -- define coordinates of rectangle\r
+  constant X_MIN : std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "0001100100";  -- 100\r
+  constant X_MAX : std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "0011001000";  -- 200\r
+  constant Y_MIN : std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "001100100";\r
+  constant Y_MAX : std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "011001000";\r
+\r
+  -- define emumerated types for state machines\r
+  type hsync_state_type is (RESET_STATE, B_STATE, C_STATE, D_STATE, E_STATE,\r
+                            pre_D_STATE, pre_B_STATE);\r
+  type vsync_state_type is (RESET_STATE, P_STATE, Q_STATE, R_STATE, S_STATE,\r
+                            pre_R_STATE, pre_P_STATE);\r
+  \r
+  --  Definitions for 7-segment display                             gfedcba\r
+  constant DIGIT_ZERO  : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000000";\r
+  constant DIGIT_ONE   : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111001";\r
+  constant DIGIT_TWO   : std_logic_vector(SEG_WIDTH-1 downto 0) := "0100100";\r
+  constant DIGIT_THREE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0110000";\r
+  constant DIGIT_FOUR  : std_logic_vector(SEG_WIDTH-1 downto 0) := "0011001";\r
+  constant DIGIT_FIVE  : std_logic_vector(SEG_WIDTH-1 downto 0) := "0010010";\r
+  constant DIGIT_SIX   : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000010";\r
+  constant DIGIT_SEVEN : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111000";\r
+  constant DIGIT_EIGHT : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000000";\r
+  constant DIGIT_NINE  : std_logic_vector(SEG_WIDTH-1 downto 0) := "0011000";\r
+  constant DIGIT_MINUS : std_logic_vector(SEG_WIDTH-1 downto 0) := "0111111";\r
+  constant DIGIT_A     : std_logic_vector(SEG_WIDTH-1 downto 0) := "0001000";\r
+  constant DIGIT_B     : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000011";\r
+  constant DIGIT_C     : std_logic_vector(SEG_WIDTH-1 downto 0) := "0110001";\r
+  constant DIGIT_D     : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000010";\r
+  constant DIGIT_E     : std_logic_vector(SEG_WIDTH-1 downto 0) := "1001111";\r
+  constant DIGIT_F     : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000111";\r
+  constant DIGIT_OFF   : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111111";\r
+ \r
+end package;\r