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[dide_16.git] / bsp4 / Designflow / src / vga_driver_ent.vhd

diff --git a/bsp4/Designflow/src/vga_driver_ent.vhd b/bsp4/Designflow/src/vga_driver_ent.vhd
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+-------------------------------------------------------------------------------
+-- Title      : vga_driver entity
+-- Project    : LU Digital Design
+-------------------------------------------------------------------------------
+-- File       : vga_driver_ent.vhd
+-- Author     : Thomas Handl
+-- Company    : TU Wien
+-- Created    : 2004-12-15
+-- Last update: 2006-02-24
+-------------------------------------------------------------------------------
+-- Description: generate vsync and hsync
+-------------------------------------------------------------------------------
+-- Copyright (c) 2004 TU Wien
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2004-12-15  1.0      handl   Created
+-- 2006-02-24  2.0      ST      revised
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- LIBRARIES
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+use work.vga_pak.all;
+
+-------------------------------------------------------------------------------
+-- ENTITY
+-------------------------------------------------------------------------------
+
+
+entity vga_driver is
+  port(clk            : in  std_logic;
+       reset          : in  std_logic;
+       column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);
+       line_counter   : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
+       h_enable       : out std_logic;
+       v_enable       : out std_logic;
+       hsync, vsync   : out std_logic;
+
+       d_hsync_state        : out hsync_state_type;
+       d_vsync_state        : out vsync_state_type;
+       d_hsync_counter      : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
+       d_vsync_counter      : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
+       d_set_hsync_counter  : out std_logic;
+       d_set_vsync_counter  : out std_logic;
+       d_set_column_counter : out std_logic;
+       d_set_line_counter   : out std_logic
+       );
+
+end vga_driver;
+
+-------------------------------------------------------------------------------
+-- END ENTITY
+-------------------------------------------------------------------------------