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[dide_16.git] / bsp4 / Designflow / src / vga_control_ent.vhd

diff --git a/bsp4/Designflow/src/vga_control_ent.vhd b/bsp4/Designflow/src/vga_control_ent.vhd
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+-------------------------------------------------------------------------------\r
+-- Title      : vga_control entity\r
+-- Project    : LU Digital Design\r
+-------------------------------------------------------------------------------\r
+-- File       : vga_control_ent.vhd\r
+-- Author     : Thomas Handl\r
+-- Company    : TU Wien\r
+-- Created    : 2004-12-15\r
+-- Last update: 2006-02-24\r
+-------------------------------------------------------------------------------\r
+-- Description: generation of colors (RGB)\r
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2004 TU Wien\r
+-------------------------------------------------------------------------------\r
+-- Revisions  :\r
+-- Date        Version  Author  Description\r
+-- 2004-12-15  1.0      handl     Created\r
+-- 2006-02-24  2.0      ST      revised\r
+-------------------------------------------------------------------------------\r
+\r
+-------------------------------------------------------------------------------\r
+-- LIBRARIES\r
+-------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.std_logic_unsigned.all;\r
+use IEEE.std_logic_arith.all;\r
+\r
+use work.vga_pak.all;\r
+\r
+-------------------------------------------------------------------------------\r
+-- ENTITY\r
+-------------------------------------------------------------------------------\r
+\r
+\r
+entity vga_control is\r
+  port(clk            : in std_logic;\r
+       reset          : in  std_logic;\r
+       column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0);\r
+       toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0);\r
+       toggle         : out std_logic;\r
+       line_counter   : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0);\r
+       v_enable       : in std_logic;\r
+       h_enable       : in std_logic;\r
+       r, g, b        : out std_logic\r
+       );\r
+\r
+end vga_control;\r
+\r
+-------------------------------------------------------------------------------\r
+-- END ENTITY\r
+-------------------------------------------------------------------------------\r