after slot5
[dide_16.git] / bsp4 / Designflow / src / vga_control_arc.vhd
diff --git a/bsp4/Designflow/src/vga_control_arc.vhd b/bsp4/Designflow/src/vga_control_arc.vhd
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+-------------------------------------------------------------------------------\r
+-- Title      : vga_control architecture\r
+-- Project    : LU Digital Design\r
+-------------------------------------------------------------------------------\r
+-- File       : vga_control.vhd\r
+-- Author     : Thomas Handl\r
+-- Company    : TU Wien\r
+-- Created    : 2004-12-15\r
+-- Last update: 2006-02-24\r
+-------------------------------------------------------------------------------\r
+-- Description: generation of colors (RGB)\r
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2004 TU Wien\r
+-------------------------------------------------------------------------------\r
+-- Revisions  :\r
+-- Date        Version  Author  Description\r
+-- 2004-12-15  1.0      handl   Created\r
+-- 2006-02-24  2.0      ST      revised\r
+-------------------------------------------------------------------------------\r
+\r
+-------------------------------------------------------------------------------\r
+-- LIBRARIES\r
+-------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.std_logic_unsigned.all;\r
+use IEEE.std_logic_arith.all;\r
+\r
+use work.vga_pak.all;\r
+\r
+-------------------------------------------------------------------------------\r
+-- ARCHITECTURE\r
+-------------------------------------------------------------------------------\r
+\r
+architecture behav of vga_control is\r
+\r
+\r
+  attribute syn_preserve          : boolean;\r
+  attribute syn_preserve of behav : architecture is true;\r
+\r
+\r
+  -- signal and constant declarations  \r
+  signal   r_next, g_next, b_next  : std_logic;                                 -- auxiliary signals for next state logic\r
+  signal   toggle_sig   : std_logic;                                            -- auxiliary signal to allow read back of toggle\r
+  signal   toggle_counter_sig  : std_logic_vector(TOG_CNT_WIDTH-1 downto 0);    -- auxiliary signal to allow read back of blinker\r
+  signal   toggle_next  : std_logic;                                            -- auxiliary signal for next state logic\r
+  signal   toggle_counter_next : std_logic_vector(TOG_CNT_WIDTH-1 downto 0);    -- auxiliary signal for next state logic\r
+  --constant HALFPERIOD   : std_logic_vector(TOG_CNT_WIDTH-1 downto 0) := "1100000000010001111011000";\r
+  constant HALFPERIOD   : std_logic_vector(TOG_CNT_WIDTH-1 downto 0) := "0000011111110010100000010"; -- 41,6666ms\r
+  --constant HALFPERIOD   : std_logic_vector(TOG_CNT_WIDTH-1 downto 0) :=   "0000101101110001101100000"; --60ms\r
+                                                                                -- define half period of toggle frequency in clock ticks\r
+\r
+begin  \r
+  -----------------------------------------------------------------------------\r
+  -- draw rectangle on screen\r
+  -----------------------------------------------------------------------------\r
+    \r
+  DRAW_SQUARE_syn: process(clk, reset)\r
+  begin\r
+    if (reset = RES_ACT) then   -- draw black screen upon reset\r
+      r <= COLR_OFF;\r
+      g <= COLR_OFF;\r
+      b <= COLR_OFF;\r
+    elsif (clk'event and clk = '1') then     -- synchronous capture\r
+      r <= r_next;\r
+      g <= g_next;\r
+      b <= b_next;\r
+    end if;\r
+  end process;\r
+\r
+\r
+  DRAW_SQUARE_next: process (column_counter, line_counter, v_enable, h_enable, toggle_sig)\r
+  begin\r
+    if v_enable = ENABLE and h_enable = ENABLE then        \r
+      if (column_counter >= X_MIN and column_counter <= X_MAX and    -- if pixel within the rectangle borders\r
+          line_counter   >= Y_MIN and line_counter   <= Y_MAX) then\r
+        r_next <= COLR_OFF;\r
+        g_next <= COLR_OFF;                                          -- ...green\r
+        b_next <= toggle_sig;                                    -- ...blue\r
+      else                                                           -- if somewhere else on screen...\r
+        r_next <= COLR_OFF;\r
+        g_next <= COLR_OFF;                                          -- ... draw background color\r
+        b_next <= COLR_OFF;\r
+      end if;\r
+    else                                                             -- if out of screen...\r
+      r_next <= COLR_OFF;\r
+      g_next <= COLR_OFF;                                            -- ... do not activate any color\r
+      b_next <= COLR_OFF;                                            --     (black screen)\r
+    end if;\r
+  end process;\r
+\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- control blinking of rectangle\r
+  -----------------------------------------------------------------------------\r
+\r
+  BLINKER_syn: process(clk, reset)\r
+  begin\r
+    if (reset = RES_ACT) then                       -- asyn reset\r
+      toggle_counter_sig  <= (others => '0');\r
+      toggle_sig  <= COLR_OFF;\r
+    elsif(clk'event and clk = '1') then             -- synchronous capture\r
+      toggle_counter_sig <= toggle_counter_next;\r
+      toggle_sig  <= toggle_next;\r
+    end if;\r
+  end process;\r
+\r
+\r
+  BLINKER_next : process(toggle_counter_sig, toggle_sig)\r
+  begin\r
+    if toggle_counter_sig >= HALFPERIOD then           -- after half period ...\r
+      toggle_counter_next <= (others => '0');          -- ... clear counter\r
+      toggle_next  <= not(toggle_sig);                 -- ... and toggle colour.\r
+    else                                               -- before half period ...\r
+      toggle_counter_next <= toggle_counter_sig + '1'; -- ... increment counter\r
+      toggle_next  <= toggle_sig;                      -- ... and hold colour\r
+    end if;\r
+  end process;\r
+\r
+\r
+-- assign auxiliary signals to module outputs\r
+toggle <= toggle_sig;\r
+toggle_counter <= toggle_counter_sig;\r
+\r
+end behav;\r
+\r
+-------------------------------------------------------------------------------\r
+-- END ARCHITECTURE\r
+-------------------------------------------------------------------------------\r