--- /dev/null
+ -------------------------------------------------------------------------------\r
+-- Title : vga architecture\r
+-- Project : LU Digital Design\r
+-------------------------------------------------------------------------------\r
+-- File : vga.vhd\r
+-- Author : Thomas Handl\r
+-- Company : TU Wien\r
+-- Created : 2004-04-07\r
+-- Last update: 2006-02-24\r
+-------------------------------------------------------------------------------\r
+-- Description: arch of top level module, the sub-modules are connected here\r
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2004 TU Wien\r
+-------------------------------------------------------------------------------\r
+-- Revisions :\r
+-- Date Version Author Description\r
+-- 2004-04-07 1.0 handl Created\r
+-- 2006-02-24 2.0 ST revised\r
+-------------------------------------------------------------------------------\r
+\r
+-------------------------------------------------------------------------------\r
+-- LIBRARIES\r
+-------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.std_logic_unsigned.all;\r
+use IEEE.std_logic_arith.all;\r
+\r
+use work.vga_pak.all; -- include package\r
+\r
+-------------------------------------------------------------------------------\r
+-- ARCHITECTURE\r
+-------------------------------------------------------------------------------\r
+\r
+architecture behav of vga is\r
+\r
+ attribute syn_preserve : boolean;\r
+ attribute syn_preserve of behav : architecture is true;\r
+\r
+\r
+-------------------------------------------------------------------------------\r
+-- component declarations for the modules\r
+-------------------------------------------------------------------------------\r
+\r
+ component vga_driver\r
+ port (\r
+ clk : in std_logic;\r
+ reset : in std_logic;\r
+ column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);\r
+ line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);\r
+ h_enable : out std_logic;\r
+ v_enable : out std_logic;\r
+ hsync : out std_logic; \r
+ vsync : out std_logic;\r
+ d_hsync_state : out hsync_state_type;\r
+ d_vsync_state : out vsync_state_type;\r
+ d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);\r
+ d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);\r
+ d_set_hsync_counter : out std_logic;\r
+ d_set_vsync_counter : out std_logic;\r
+ d_set_column_counter : out std_logic;\r
+ d_set_line_counter : out std_logic);\r
+ end component;\r
+\r
+\r
+ component vga_control\r
+ port (\r
+ clk : in std_logic;\r
+ reset : in std_logic;\r
+ column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0);\r
+ line_counter : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0);\r
+ h_enable : in std_logic;\r
+ v_enable : in std_logic;\r
+ toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0);\r
+ toggle : out std_logic;\r
+ r, g, b : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component board_driver\r
+ port (\r
+ reset : in std_logic;\r
+ seven_seg : out std_logic_vector(2*SEG_WIDTH-1 downto 0));\r
+ end component;\r
+\r
+\r
+-- declare signals needed for internal wiring of these components later\r
+ signal column_counter_sig : std_logic_vector(COL_CNT_WIDTH-1 downto 0);\r
+ signal line_counter_sig : std_logic_vector(LINE_CNT_WIDTH-1 downto 0);\r
+ signal h_enable_sig : std_logic;\r
+ signal v_enable_sig : std_logic;\r
+ signal r_sig, g_sig, b_sig : std_logic;\r
+ signal hsync_sig, vsync_sig : std_logic;\r
+ \r
+-- declare signals needed for prolongation of reset\r
+ signal dly_counter : std_logic_vector(1 downto 0);\r
+ signal dly_counter_next : std_logic_vector(1 downto 0);\r
+ constant MAX_DLY : std_logic_vector(1 downto 0) := "11";\r
+ signal reset_dly : std_logic; --\r
+ signal safe_reset : std_logic; \r
+\r
+\r
+-------------------------------------------------------------------------------\r
+-- prolong duration of reset to prevent glitches at power-up\r
+-------------------------------------------------------------------------------\r
+\r
+begin\r
+\r
+ DELAY_RESET_syn : process(clk_pin) -- synchronous capture\r
+ begin\r
+ if clk_pin'event and clk_pin = '1' then -- upon rising clock\r
+ dly_counter <= dly_counter_next; -- ... capture new counter value\r
+ end if;\r
+ end process;\r
+\r
+ DELAY_RESET_next : process(dly_counter, reset_pin) -- next state logic\r
+ begin\r
+ if reset_pin = RES_ACT then -- upon reset\r
+ dly_counter_next <= (others => '0'); -- ...clear dly counter\r
+ elsif dly_counter < MAX_DLY then -- if no oflo\r
+ dly_counter_next <= dly_counter + '1'; -- ...increment dly counter\r
+ else \r
+ dly_counter_next <= dly_counter; -- freeze dly counter when oflo\r
+ end if;\r
+ end process;\r
+ \r
+ DELAY_RESET_out: process(dly_counter)\r
+ begin\r
+ if dly_counter < MAX_DLY then -- until dly counter reaches maximum\r
+ reset_dly <= RES_ACT; -- ...activate delayed reset signal\r
+ else -- upon counter oflo \r
+ reset_dly <= not(RES_ACT); -- ...finally deactivate delayed reset\r
+ end if;\r
+ end process;\r
+\r
+\r
+\r
+ COMBINE_RESET: process(reset_pin, reset_dly) -- generate "safe" reset signal\r
+ begin\r
+ if reset_pin = RES_ACT or reset_dly = RES_ACT then -- ...by combining delayed reset with non-delayed reset input \r
+ safe_reset <= RES_ACT;\r
+ else\r
+ safe_reset <= not(RES_ACT);\r
+ end if;\r
+ end process;\r
+\r
+\r
+-------------------------------------------------------------------------------\r
+-- instantiate the components and connect to internal and external signals\r
+-------------------------------------------------------------------------------\r
+\r
+\r
+board_driver_unit : board_driver\r
+ port map (\r
+ reset => safe_reset,\r
+ seven_seg => seven_seg_pin);\r
+\r
+\r
+vga_driver_unit : vga_driver\r
+ port map (\r
+ clk => clk_pin,\r
+ reset => safe_reset,\r
+ column_counter => column_counter_sig,\r
+ line_counter => line_counter_sig,\r
+ h_enable => h_enable_sig,\r
+ v_enable => v_enable_sig,\r
+ hsync => hsync_sig,\r
+ vsync => vsync_sig,\r
+ d_hsync_state => d_hsync_state,\r
+ d_vsync_state => d_vsync_state,\r
+ d_hsync_counter => d_hsync_counter,\r
+ d_vsync_counter => d_vsync_counter,\r
+ d_set_hsync_counter => d_set_hsync_counter,\r
+ d_set_vsync_counter => d_set_vsync_counter,\r
+ d_set_column_counter => d_set_column_counter,\r
+ d_set_line_counter => d_set_line_counter);\r
+\r
+-- make the wiring for hsync and vsync pins \r
+-- (pin is output only => internal _sig version required to allow readback of signal)\r
+ vsync_pin <= vsync_sig;\r
+ hsync_pin <= hsync_sig;\r
+\r
+\r
+ vga_control_unit : vga_control\r
+ port map (\r
+ clk => clk_pin,\r
+ reset => safe_reset,\r
+ column_counter => column_counter_sig,\r
+ line_counter => line_counter_sig,\r
+ h_enable => h_enable_sig,\r
+ v_enable => v_enable_sig,\r
+ toggle_counter => d_toggle_counter,\r
+ toggle => d_toggle,\r
+ r => r_sig,\r
+ g => g_sig,\r
+ b => b_sig);\r
+\r
+-- make the wiring for RGB pins: drive all pins for same color from one source ("8 color mode")\r
+ r0_pin <= r_sig; r1_pin <= r_sig; r2_pin <= r_sig;\r
+ g0_pin <= g_sig; g1_pin <= g_sig; g2_pin <= g_sig;\r
+ b0_pin <= b_sig; b1_pin <= b_sig;\r
+\r
+\r
+-- make extra pin connections for debug signals\r
+ d_hsync <= hsync_sig; -- make duplicate of signal for debug connector\r
+ d_vsync <= vsync_sig; -- make duplicate of signal for debug connector\r
+ d_column_counter <= column_counter_sig;\r
+ d_line_counter <= line_counter_sig;\r
+ d_h_enable <= h_enable_sig;\r
+ d_v_enable <= v_enable_sig;\r
+ d_r <= r_sig;\r
+ d_g <= g_sig;\r
+ d_b <= b_sig;\r
+ d_state_clk <= clk_pin; -- make duplicate of signal for debug connector\r
+\r
+ \r
+end behav;\r
+\r
+-------------------------------------------------------------------------------\r
+-- END ARCHITECTURE\r
+-------------------------------------------------------------------------------\r
projects / dide_16.git / blobdiff