after slot5
[dide_16.git] / bsp4 / Designflow / src / board_driver_ent.vhd
diff --git a/bsp4/Designflow/src/board_driver_ent.vhd b/bsp4/Designflow/src/board_driver_ent.vhd
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+-------------------------------------------------------------------------------\r
+-- Title      : board_driver entity\r
+-- Project    : LU Digital Design\r
+-------------------------------------------------------------------------------\r
+-- File       : board_driver_ent.vhd\r
+-- Author     : Thomas Handl\r
+-- Company    : TU Wien\r
+-- Created    : 2004-12-15\r
+-- Last update: 2006-02-24\r
+-------------------------------------------------------------------------------\r
+-- Description: display number on 7-segment display\r
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2004 TU Wien\r
+-------------------------------------------------------------------------------\r
+-- Revisions  :\r
+-- Date        Version  Author  Description\r
+-- 2004-12-15  1.0      handl   Created\r
+-- 2006-02-24  2.0      ST      revised\r
+-------------------------------------------------------------------------------\r
+\r
+-------------------------------------------------------------------------------\r
+-- LIBRARIES\r
+-------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.std_logic_unsigned.all;\r
+use IEEE.std_logic_arith.all;\r
+\r
+use work.vga_pak.all;\r
+\r
+-------------------------------------------------------------------------------\r
+-- ENTITY\r
+-------------------------------------------------------------------------------\r
+\r
+entity board_driver is\r
+  \r
+  port (\r
+        reset      : in  std_logic;\r
+        seven_seg  : out std_logic_vector(2*SEG_WIDTH-1 downto 0)\r
+        );                       \r
+end board_driver;\r