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[dide_16.git] / bsp4 / Designflow / src / board_driver_arc.vhd

diff --git a/bsp4/Designflow/src/board_driver_arc.vhd b/bsp4/Designflow/src/board_driver_arc.vhd
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+-------------------------------------------------------------------------------\r
+-- Title      : board_driver architecture\r
+-- Project    : LU Digital Design\r
+-------------------------------------------------------------------------------\r
+-- File       : board_driver.vhd\r
+-- Author     : Thomas Handl\r
+-- Company    : TU Wien\r
+-- Created    : 2004-12-15\r
+-- Last update: 2006-02-24\r
+-------------------------------------------------------------------------------\r
+-- Description: display number on 7-segment display\r
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2004 TU Wien\r
+-------------------------------------------------------------------------------\r
+-- Revisions  :\r
+-- Date        Version  Author  Description\r
+-- 2004-12-15  1.0      handl   Created\r
+-- 2006-02-24  2.0      ST      revised\r
+-------------------------------------------------------------------------------\r
+\r
+-------------------------------------------------------------------------------\r
+-- LIBRARIES\r
+-------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.std_logic_unsigned.all;\r
+use IEEE.std_logic_arith.all;\r
+\r
+use work.vga_pak.all;\r
+\r
+-------------------------------------------------------------------------------\r
+-- ARCHITECTURE\r
+-------------------------------------------------------------------------------\r
+\r
+\r
+architecture behav of board_driver is\r
+\r
+  attribute syn_preserve          : boolean;\r
+  attribute syn_preserve of behav : architecture is true;\r
+\r
+\r
+  signal   display_value  : std_logic_vector(2*BCD_WIDTH-1 downto 0);\r
+  signal   ten_value      : std_logic_vector(BCD_WIDTH-1 downto 0);\r
+  signal   one_value      : std_logic_vector(BCD_WIDTH-1 downto 0);\r
+  signal   digit_left     : std_logic_vector(SEG_WIDTH-1 downto 0);\r
+  signal   digit_right    : std_logic_vector(SEG_WIDTH-1 downto 0);\r
+\r
+begin\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- generate control data\r
+  -----------------------------------------------------------------------------\r
+\r
+\r
+  display_value <= "00000001";                                 -- vector of two BCD coded numbers to be displayed\r
+  one_value <= display_value(BCD_WIDTH-1 downto 0);            -- BCD number to be displayed in right digit\r
+  ten_value <= display_value(2*BCD_WIDTH-1 downto BCD_WIDTH);  -- BCD number to be displayed in left digit\r
+\r
+\r
+  SEG_DATA: process(reset, one_value, ten_value)\r
+  begin\r
+    if (reset = RES_ACT) then                     -- upon reset\r
+      digit_left  <= DIGIT_OFF;                   -- ... switch off display\r
+      digit_right <= DIGIT_OFF;\r
+    else                                          -- during operation\r
+      case one_value is                           -- ...display "one" position according\r
+        when "0000" => digit_right <= DIGIT_ZERO; -- ...to translation table\r
+        when "0001" => digit_right <= DIGIT_ONE;\r
+        when "0010" => digit_right <= DIGIT_TWO;\r
+        when "0011" => digit_right <= DIGIT_THREE;\r
+        when "0100" => digit_right <= DIGIT_FOUR;\r
+        when "0101" => digit_right <= DIGIT_FIVE;\r
+        when "0110" => digit_right <= DIGIT_SIX;\r
+        when "0111" => digit_right <= DIGIT_SEVEN;\r
+        when "1000" => digit_right <= DIGIT_EIGHT;\r
+        when "1001" => digit_right <= DIGIT_NINE;\r
+        when others => digit_right <= DIGIT_F;    -- use "F" as overflow\r
+      end case;\r
+\r
+      case ten_value is                           -- same for "ten" position\r
+        when "0000" => digit_left <= DIGIT_ZERO;\r
+        when "0001" => digit_left <= DIGIT_ONE;\r
+        when "0010" => digit_left <= DIGIT_TWO;\r
+        when "0011" => digit_left <= DIGIT_THREE;\r
+        when "0100" => digit_left <= DIGIT_FOUR;\r
+        when "0101" => digit_left <= DIGIT_FIVE;\r
+        when "0110" => digit_left <= DIGIT_SIX;\r
+        when "0111" => digit_left <= DIGIT_SEVEN;\r
+        when "1000" => digit_left <= DIGIT_EIGHT;\r
+        when "1001" => digit_left <= DIGIT_NINE;\r
+        when others => digit_left <= DIGIT_F;\r
+      end case;\r
+    end if;\r
+  end process;\r
+\r
+\r
+-- combine the two digits to one bus\r
+  seven_seg(SEG_WIDTH-1 downto 0)  <= digit_right;\r
+  seven_seg(2*SEG_WIDTH-1 downto SEG_WIDTH) <= digit_left;\r
+  \r
+end behav;\r