after slot5
[dide_16.git] / bsp4 / Designflow / sim / post / work / @_opt / voptbrh2yj
diff --git a/bsp4/Designflow/sim/post/work/@_opt/voptbrh2yj b/bsp4/Designflow/sim/post/work/@_opt/voptbrh2yj
new file mode 100644 (file)
index 0000000..d22e072
--- /dev/null
@@ -0,0 +1,148 @@
+m255
+K3
+13
+cModel Technology
+Z0 d/homes/burban/didelu/dide_16/bsp4/Designflow/sim/post
+T_opt
+Z1 VEaAWm1d_JS=VNkklOXhG;0
+Z2 04 12 0 work vga_conf_pos 1
+Z3 =1-0015609ed0a8-4af05b46-4068a-7b76
+Z4 o-quiet -auto_acc_if_foreign -work work -sdftyp /vga_unit=/homes/burban/didelu/dide_16/bsp4/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo -suppress 1948
+Z5 n@_opt
+Z6 OE;O;6.5b;42
+Evga
+Z7 w1257265900
+Z8 DPx17 __model_tech/ieee 16 vital_primitives 0 22 E9g6AWKAc2T]enMfl94If3
+Z9 DPx20 __model_tech/stratix 17 stratix_atom_pack 0 22 4LU4R]0>3N6GcAdgd1O1R2
+Z10 DPx17 __model_tech/ieee 12 vital_timing 0 22 OBWK>;kUYmkG<OChK2lhV1
+Z11 DPx20 __model_tech/stratix 18 stratix_components 0 22 ETJi=`V@8?ceQEj0KODmn3
+Z12 DPx17 __model_tech/ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
+32
+Z13 8/homes/burban/didelu/dide_16/bsp4/Designflow/ppr/sim/simulation/modelsim/vga.vho
+Z14 F/homes/burban/didelu/dide_16/bsp4/Designflow/ppr/sim/simulation/modelsim/vga.vho
+l0
+L33
+Z15 Va^A3`oj7W2X29O[KC68:E3
+Z16 OE;C;6.5b;42
+Z17 o-work work
+Z18 tExplicit 1
+Z19 !s100 JmIRf5hghCim]`W8beHGP0
+Astructure
+Z20 DEx20 __model_tech/stratix 10 stratix_io 0 22 8g8W4@DX]PW8dgJFjd5lT1
+Z21 DEx20 __model_tech/stratix 13 stratix_lcell 0 22 aWl_l1>i5>lzY<SO57h5o1
+R8
+R9
+R10
+R11
+R12
+Z22 DEx58 /homes/burban/didelu/dide_16/bsp4/Designflow/sim/post/work 3 vga 0 22 a^A3`oj7W2X29O[KC68:E3
+32
+Z23 Mx6 17 __model_tech/ieee 14 std_logic_1164
+Z24 Mx5 20 __model_tech/stratix 18 stratix_components
+Z25 Mx4 17 __model_tech/ieee 12 vital_timing
+Z26 Mx3 16 __model_tech/std 6 textio
+Z27 Mx2 20 __model_tech/stratix 17 stratix_atom_pack
+Z28 Mx1 17 __model_tech/ieee 16 vital_primitives
+l339
+L71
+Z29 V]Wm516:I9;]lA9UPJ_ON=3
+R16
+R17
+R18
+Z30 !s100 @2=YGQ1l@859QgkB=LQ;73
+Cvga_conf_pos
+R8
+R9
+R10
+R11
+R22
+DAx58 /homes/burban/didelu/dide_16/bsp4/Designflow/sim/post/work 10 vga_pos_tb 9 structure 22 2H0Zl8k[9mYf8bN=NCbeH0
+Z31 DPx58 /homes/burban/didelu/dide_16/bsp4/Designflow/sim/post/work 7 vga_pak 0 22 HkmzP=gd;mD@MOhh4AYKl3
+Z32 DPx17 __model_tech/ieee 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2
+Z33 DPx17 __model_tech/ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90
+R12
+Z34 DEx58 /homes/burban/didelu/dide_16/bsp4/Designflow/sim/post/work 10 vga_pos_tb 0 22 WYVDk8:IlXF:G=gkK18_k0
+32
+Z35 Mx9 17 __model_tech/ieee 14 std_logic_1164
+Z36 Mx8 17 __model_tech/ieee 18 std_logic_unsigned
+Z37 Mx7 17 __model_tech/ieee 15 std_logic_arith
+Z38 Mx6 58 /homes/burban/didelu/dide_16/bsp4/Designflow/sim/post/work 7 vga_pak
+R24
+R25
+R26
+R27
+R28
+Z39 astructure
+Z40 evga_pos_tb
+Z41 w1255952276
+Z42 8/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pos_tb.vhd
+Z43 F/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pos_tb.vhd
+l0
+L190
+Z44 V0i2Wgcf;160Sh<_O1]Yd91
+R16
+R17
+R18
+Z45 !s100 5AFP2EDWmkBg2TkYkScac0
+Pvga_pak
+R32
+R33
+R12
+32
+Z46 Mx3 17 __model_tech/ieee 14 std_logic_1164
+Mx2 17 __model_tech/ieee 18 std_logic_unsigned
+Z47 Mx1 17 __model_tech/ieee 15 std_logic_arith
+Z48 w1257265128
+Z49 8/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd
+Z50 F/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd
+l0
+L35
+Z51 VHkmzP=gd;mD@MOhh4AYKl3
+R16
+R17
+R18
+Z52 !s100 VL:Z2?FJISz9N5>XaK:5k0
+Evga_pos_tb
+R41
+R31
+R32
+R33
+R12
+32
+R42
+R43
+l0
+L37
+Z53 VWYVDk8:IlXF:G=gkK18_k0
+R16
+R17
+R18
+Z54 !s100 ?:YH_R3N79K7J0L`IT49_0
+Astructure
+R8
+R9
+R10
+R11
+R22
+R31
+R32
+R33
+R12
+R34
+32
+R35
+R36
+R37
+R38
+R24
+R25
+R26
+R27
+R28
+l101
+L45
+Z55 V2H0Zl8k[9mYf8bN=NCbeH0
+R16
+R17
+R18
+Z56 !s100 T_8dcPYGCmK@^6g;3L5;b0