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[dide_16.git] / bsp4 / Designflow / ppr / sim / vga.map.summary

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+Analysis & Synthesis Status : Successful - Tue Nov  3 17:30:34 2009
+Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
+Revision Name : vga
+Top-level Entity Name : vga
+Family : Stratix
+Total logic elements : 175
+Total pins : 117
+Total virtual pins : 0
+Total memory bits : 0
+DSP block 9-bit elements : 0
+Total PLLs : 0
+Total DLLs : 0