--- /dev/null
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions
+// and other software and tools, and its AMPP partner logic
+// functions, and any output files from any of the foregoing
+// (including device programming or simulation files), and any
+// associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License
+// Subscription Agreement, Altera MegaCore Function License
+// Agreement, or other applicable license agreement, including,
+// without limitation, that your use is for the sole purpose of
+// programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details.
+
+
+//
+// Device: Altera EP1S25F672C6 Package FBGA672
+//
+
+//
+// This SDF file should be used for ModelSim (VHDL) only
+//
+
+(DELAYFILE
+ (SDFVERSION "2.1")
+ (DESIGN "vga")
+ (DATE "11/03/2009 17:31:40")
+ (VENDOR "Altera")
+ (PROGRAM "Quartus II")
+ (VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version")
+ (DIVIDER .)
+ (TIMESCALE 1 ps)
+
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE clk_pin_in.inst1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH padio combout (868:868:868) (868:868:868))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE reset_pin_in.inst1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH padio combout (868:868:868) (868:868:868))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\dly_counter_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (5525:5525:5525) (5525:5525:5525))
+ (PORT datac (992:992:992) (992:992:992))
+ (PORT datad (461:461:461) (461:461:461))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\dly_counter_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2472:2472:2472) (2472:2472:2472))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\dly_counter_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (446:446:446) (446:446:446))
+ (PORT datac (655:655:655) (655:655:655))
+ (PORT datad (5530:5530:5530) (5530:5530:5530))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\dly_counter_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2472:2472:2472) (2472:2472:2472))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (451:451:451) (451:451:451))
+ (PORT datac (652:652:652) (652:652:652))
+ (PORT datad (5528:5528:5528) (5528:5528:5528))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2472:2472:2472) (2472:2472:2472))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (2040:2040:2040) (2040:2040:2040))
+ (PORT datad (1275:1275:1275) (1275:1275:1275))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (2130:2130:2130) (2130:2130:2130))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2448:2448:2448) (2448:2448:2448))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (423:423:423) (423:423:423))
+ (PORT datac (1610:1610:1610) (1610:1610:1610))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1457:1457:1457) (1457:1457:1457))
+ (PORT datac (1700:1700:1700) (1700:1700:1700))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2413:2413:2413) (2413:2413:2413))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (419:419:419) (419:419:419))
+ (PORT datac (1609:1609:1609) (1609:1609:1609))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1457:1457:1457) (1457:1457:1457))
+ (PORT datac (1699:1699:1699) (1699:1699:1699))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2413:2413:2413) (2413:2413:2413))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (444:444:444) (444:444:444))
+ (PORT datac (1607:1607:1607) (1607:1607:1607))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1457:1457:1457) (1457:1457:1457))
+ (PORT datac (1697:1697:1697) (1697:1697:1697))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2413:2413:2413) (2413:2413:2413))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datac (1606:1606:1606) (1606:1606:1606))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1457:1457:1457) (1457:1457:1457))
+ (PORT datac (1696:1696:1696) (1696:1696:1696))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2413:2413:2413) (2413:2413:2413))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (1605:1605:1605) (1605:1605:1605))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1457:1457:1457) (1457:1457:1457))
+ (PORT datac (1695:1695:1695) (1695:1695:1695))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2413:2413:2413) (2413:2413:2413))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (420:420:420) (420:420:420))
+ (PORT datac (1592:1592:1592) (1592:1592:1592))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1457:1457:1457) (1457:1457:1457))
+ (PORT datac (1682:1682:1682) (1682:1682:1682))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2413:2413:2413) (2413:2413:2413))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (422:422:422) (422:422:422))
+ (PORT datac (1595:1595:1595) (1595:1595:1595))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1457:1457:1457) (1457:1457:1457))
+ (PORT datac (1685:1685:1685) (1685:1685:1685))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2413:2413:2413) (2413:2413:2413))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datac (1598:1598:1598) (1598:1598:1598))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_7_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1457:1457:1457) (1457:1457:1457))
+ (PORT datac (1688:1688:1688) (1688:1688:1688))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2413:2413:2413) (2413:2413:2413))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (1601:1601:1601) (1601:1601:1601))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_8_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1457:1457:1457) (1457:1457:1457))
+ (PORT datac (1691:1691:1691) (1691:1691:1691))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2413:2413:2413) (2413:2413:2413))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1603:1603:1603) (1603:1603:1603))
+ (PORT datad (432:432:432) (432:432:432))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_9_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1457:1457:1457) (1457:1457:1457))
+ (PORT datac (1693:1693:1693) (1693:1693:1693))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2413:2413:2413) (2413:2413:2413))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1157:1157:1157) (1157:1157:1157))
+ (PORT datab (1141:1141:1141) (1141:1141:1141))
+ (PORT datac (1164:1164:1164) (1164:1164:1164))
+ (PORT datad (1107:1107:1107) (1107:1107:1107))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (577:577:577) (577:577:577))
+ (PORT datab (663:663:663) (663:663:663))
+ (PORT datac (659:659:659) (659:659:659))
+ (PORT datad (1051:1051:1051) (1051:1051:1051))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|G_2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (2259:2259:2259) (2259:2259:2259))
+ (PORT datab (2033:2033:2033) (2033:2033:2033))
+ (PORT datac (1799:1799:1799) (1799:1799:1799))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_7\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (664:664:664) (664:664:664))
+ (PORT datab (622:622:622) (622:622:622))
+ (PORT datac (973:973:973) (973:973:973))
+ (PORT datad (966:966:966) (966:966:966))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (638:638:638) (638:638:638))
+ (PORT datab (641:641:641) (641:641:641))
+ (PORT datac (994:994:994) (994:994:994))
+ (PORT datad (671:671:671) (671:671:671))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (710:710:710) (710:710:710))
+ (PORT datab (341:341:341) (341:341:341))
+ (PORT datac (708:708:708) (708:708:708))
+ (PORT datad (347:347:347) (347:347:347))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (663:663:663) (663:663:663))
+ (PORT datab (659:659:659) (659:659:659))
+ (PORT datac (652:652:652) (652:652:652))
+ (PORT datad (625:625:625) (625:625:625))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (715:715:715) (715:715:715))
+ (PORT datab (694:694:694) (694:694:694))
+ (PORT datac (991:991:991) (991:991:991))
+ (PORT datad (964:964:964) (964:964:964))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (665:665:665) (665:665:665))
+ (PORT datab (343:343:343) (343:343:343))
+ (PORT datac (638:638:638) (638:638:638))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (636:636:636) (636:636:636))
+ (PORT datab (631:631:631) (631:631:631))
+ (PORT datac (612:612:612) (612:612:612))
+ (PORT datad (609:609:609) (609:609:609))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (632:632:632) (632:632:632))
+ (PORT datab (631:631:631) (631:631:631))
+ (PORT datad (625:625:625) (625:625:625))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_1\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (593:593:593) (593:593:593))
+ (PORT datac (605:605:605) (605:605:605))
+ (PORT datad (675:675:675) (675:675:675))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (2211:2211:2211) (2211:2211:2211))
+ (PORT datad (2256:2256:2256) (2256:2256:2256))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2314:2314:2314) (2314:2314:2314))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2413:2413:2413) (2413:2413:2413))
+ (PORT ena (1639:1639:1639) (1639:1639:1639))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (850:850:850) (850:850:850))
+ (PORT datab (344:344:344) (344:344:344))
+ (PORT datac (601:601:601) (601:601:601))
+ (PORT datad (446:446:446) (446:446:446))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2314:2314:2314) (2314:2314:2314))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2413:2413:2413) (2413:2413:2413))
+ (PORT ena (1639:1639:1639) (1639:1639:1639))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (634:634:634) (634:634:634))
+ (PORT datab (625:625:625) (625:625:625))
+ (PORT datac (607:607:607) (607:607:607))
+ (PORT datad (621:621:621) (621:621:621))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_next_1_sqmuxa_2_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (375:375:375) (375:375:375))
+ (PORT datab (429:429:429) (429:429:429))
+ (PORT datac (366:366:366) (366:366:366))
+ (PORT datad (355:355:355) (355:355:355))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (359:359:359) (359:359:359))
+ (PORT datab (344:344:344) (344:344:344))
+ (PORT datac (1188:1188:1188) (1188:1188:1188))
+ (PORT datad (1338:1338:1338) (1338:1338:1338))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1278:1278:1278) (1278:1278:1278))
+ (PORT sclr (2572:2572:2572) (2572:2572:2572))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2413:2413:2413) (2413:2413:2413))
+ (PORT ena (1081:1081:1081) (1081:1081:1081))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_next_1_sqmuxa_1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (456:456:456) (456:456:456))
+ (PORT datab (348:348:348) (348:348:348))
+ (PORT datac (366:366:366) (366:366:366))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_3_0_0_0__g0_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1806:1806:1806) (1806:1806:1806))
+ (PORT datab (917:917:917) (917:917:917))
+ (PORT datac (370:370:370) (370:370:370))
+ (PORT datad (926:926:926) (926:926:926))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1435:1435:1435) (1435:1435:1435))
+ (PORT datac (1775:1775:1775) (1775:1775:1775))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1824:1824:1824) (1824:1824:1824))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2472:2472:2472) (2472:2472:2472))
+ (PORT ena (1916:1916:1916) (1916:1916:1916))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1404:1404:1404) (1404:1404:1404))
+ (PORT datad (709:709:709) (709:709:709))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1824:1824:1824) (1824:1824:1824))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2472:2472:2472) (2472:2472:2472))
+ (PORT ena (1916:1916:1916) (1916:1916:1916))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_next_1_sqmuxa_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (473:473:473) (473:473:473))
+ (PORT datab (975:975:975) (975:975:975))
+ (PORT datac (5544:5544:5544) (5544:5544:5544))
+ (PORT datad (1496:1496:1496) (1496:1496:1496))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (630:630:630) (630:630:630))
+ (PORT datab (629:629:629) (629:629:629))
+ (PORT datad (609:609:609) (609:609:609))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (376:376:376) (376:376:376))
+ (PORT datab (431:431:431) (431:431:431))
+ (PORT datac (599:599:599) (599:599:599))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2314:2314:2314) (2314:2314:2314))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2413:2413:2413) (2413:2413:2413))
+ (PORT ena (1639:1639:1639) (1639:1639:1639))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_next_0_sqmuxa_1_1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (966:966:966) (966:966:966))
+ (PORT datab (619:619:619) (619:619:619))
+ (PORT datac (5548:5548:5548) (5548:5548:5548))
+ (PORT datad (1290:1290:1290) (1290:1290:1290))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (461:461:461) (461:461:461))
+ (PORT datad (625:625:625) (625:625:625))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2608:2608:2608) (2608:2608:2608))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2406:2406:2406) (2406:2406:2406))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (942:942:942) (942:942:942))
+ (PORT datab (676:676:676) (676:676:676))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (540:540:540) (540:540:540))
+ (PORT datad (630:630:630) (630:630:630))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2608:2608:2608) (2608:2608:2608))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2406:2406:2406) (2406:2406:2406))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1196:1196:1196) (1196:1196:1196))
+ (PORT datab (1380:1380:1380) (1380:1380:1380))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1222:1222:1222) (1222:1222:1222))
+ (PORT datab (1109:1109:1109) (1109:1109:1109))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1155:1155:1155) (1155:1155:1155))
+ (PORT datab (414:414:414) (414:414:414))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1328:1328:1328) (1328:1328:1328))
+ (PORT datad (340:340:340) (340:340:340))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2614:2614:2614) (2614:2614:2614))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2403:2403:2403) (2403:2403:2403))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (684:684:684) (684:684:684))
+ (PORT datab (688:688:688) (688:688:688))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (947:947:947) (947:947:947))
+ (PORT datab (1122:1122:1122) (1122:1122:1122))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (935:935:935) (935:935:935))
+ (PORT datad (352:352:352) (352:352:352))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2653:2653:2653) (2653:2653:2653))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2406:2406:2406) (2406:2406:2406))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (628:628:628) (628:628:628))
+ (PORT datab (416:416:416) (416:416:416))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (352:352:352) (352:352:352))
+ (PORT datab (920:920:920) (920:920:920))
+ (PORT datac (1883:1883:1883) (1883:1883:1883))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_7_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2406:2406:2406) (2406:2406:2406))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1175:1175:1175) (1175:1175:1175))
+ (PORT datab (1203:1203:1203) (1203:1203:1203))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (938:938:938) (938:938:938))
+ (PORT datad (1031:1031:1031) (1031:1031:1031))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2653:2653:2653) (2653:2653:2653))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2406:2406:2406) (2406:2406:2406))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_1\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (680:680:680) (680:680:680))
+ (PORT datad (965:965:965) (965:965:965))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (450:450:450) (450:450:450))
+ (PORT datac (682:682:682) (682:682:682))
+ (PORT datad (1077:1077:1077) (1077:1077:1077))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (452:452:452) (452:452:452))
+ (PORT datab (445:445:445) (445:445:445))
+ (PORT datac (373:373:373) (373:373:373))
+ (PORT datad (339:339:339) (339:339:339))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datad (1145:1145:1145) (1145:1145:1145))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (921:921:921) (921:921:921))
+ (PORT datac (1883:1883:1883) (1883:1883:1883))
+ (PORT datad (1026:1026:1026) (1026:1026:1026))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_8_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2406:2406:2406) (2406:2406:2406))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (442:442:442) (442:442:442))
+ (PORT datad (941:941:941) (941:941:941))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (936:936:936) (936:936:936))
+ (PORT datad (352:352:352) (352:352:352))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_9_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2653:2653:2653) (2653:2653:2653))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2406:2406:2406) (2406:2406:2406))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglto9\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (559:559:559) (559:559:559))
+ (PORT datab (953:953:953) (953:953:953))
+ (PORT datac (1003:1003:1003) (1003:1003:1003))
+ (PORT datad (1073:1073:1073) (1073:1073:1073))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (640:640:640) (640:640:640))
+ (PORT datad (1035:1035:1035) (1035:1035:1035))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2608:2608:2608) (2608:2608:2608))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2406:2406:2406) (2406:2406:2406))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (857:857:857) (857:857:857))
+ (PORT datad (626:626:626) (626:626:626))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2608:2608:2608) (2608:2608:2608))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2406:2406:2406) (2406:2406:2406))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un5_v_enablelto3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (694:694:694) (694:694:694))
+ (PORT datab (446:446:446) (446:446:446))
+ (PORT datac (460:460:460) (460:460:460))
+ (PORT datad (457:457:457) (457:457:457))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un5_v_enablelto5_0\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1133:1133:1133) (1133:1133:1133))
+ (PORT datad (969:969:969) (969:969:969))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un5_v_enablelto7\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (565:565:565) (565:565:565))
+ (PORT datab (530:530:530) (530:530:530))
+ (PORT datac (964:964:964) (964:964:964))
+ (PORT datad (1068:1068:1068) (1068:1068:1068))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1959:1959:1959) (1959:1959:1959))
+ (PORT datab (599:599:599) (599:599:599))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1763:1763:1763) (1763:1763:1763))
+ (PORT datab (423:423:423) (423:423:423))
+ (PORT datac (1251:1251:1251) (1251:1251:1251))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1470:1470:1470) (1470:1470:1470))
+ (PORT datac (1341:1341:1341) (1341:1341:1341))
+ (PORT sclr (1340:1340:1340) (1340:1340:1340))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2476:2476:2476) (2476:2476:2476))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (419:419:419) (419:419:419))
+ (PORT datac (1249:1249:1249) (1249:1249:1249))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1470:1470:1470) (1470:1470:1470))
+ (PORT datac (1339:1339:1339) (1339:1339:1339))
+ (PORT sclr (1340:1340:1340) (1340:1340:1340))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2476:2476:2476) (2476:2476:2476))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (444:444:444) (444:444:444))
+ (PORT datac (1248:1248:1248) (1248:1248:1248))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1470:1470:1470) (1470:1470:1470))
+ (PORT datac (1338:1338:1338) (1338:1338:1338))
+ (PORT sclr (1340:1340:1340) (1340:1340:1340))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2476:2476:2476) (2476:2476:2476))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datac (1247:1247:1247) (1247:1247:1247))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1470:1470:1470) (1470:1470:1470))
+ (PORT datac (1337:1337:1337) (1337:1337:1337))
+ (PORT sclr (1340:1340:1340) (1340:1340:1340))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2476:2476:2476) (2476:2476:2476))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (1246:1246:1246) (1246:1246:1246))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1470:1470:1470) (1470:1470:1470))
+ (PORT datac (1336:1336:1336) (1336:1336:1336))
+ (PORT sclr (1340:1340:1340) (1340:1340:1340))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2476:2476:2476) (2476:2476:2476))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (420:420:420) (420:420:420))
+ (PORT datac (1233:1233:1233) (1233:1233:1233))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1470:1470:1470) (1470:1470:1470))
+ (PORT datac (1323:1323:1323) (1323:1323:1323))
+ (PORT sclr (1340:1340:1340) (1340:1340:1340))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2476:2476:2476) (2476:2476:2476))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_6\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (945:945:945) (945:945:945))
+ (PORT datab (922:922:922) (922:922:922))
+ (PORT datac (928:928:928) (928:928:928))
+ (PORT datad (960:960:960) (960:960:960))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (422:422:422) (422:422:422))
+ (PORT datac (1235:1235:1235) (1235:1235:1235))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1470:1470:1470) (1470:1470:1470))
+ (PORT datac (1325:1325:1325) (1325:1325:1325))
+ (PORT sclr (1340:1340:1340) (1340:1340:1340))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2476:2476:2476) (2476:2476:2476))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datac (1238:1238:1238) (1238:1238:1238))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_7_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1470:1470:1470) (1470:1470:1470))
+ (PORT datac (1328:1328:1328) (1328:1328:1328))
+ (PORT sclr (1340:1340:1340) (1340:1340:1340))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2476:2476:2476) (2476:2476:2476))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (1241:1241:1241) (1241:1241:1241))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_8_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1470:1470:1470) (1470:1470:1470))
+ (PORT datac (1331:1331:1331) (1331:1331:1331))
+ (PORT sclr (1340:1340:1340) (1340:1340:1340))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2476:2476:2476) (2476:2476:2476))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_5\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (997:997:997) (997:997:997))
+ (PORT datab (582:582:582) (582:582:582))
+ (PORT datac (918:918:918) (918:918:918))
+ (PORT datad (591:591:591) (591:591:591))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (625:625:625) (625:625:625))
+ (PORT datab (340:340:340) (340:340:340))
+ (PORT datac (990:990:990) (990:990:990))
+ (PORT datad (350:350:350) (350:350:350))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|G_16\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (355:355:355) (355:355:355))
+ (PORT datab (1687:1687:1687) (1687:1687:1687))
+ (PORT datac (1443:1443:1443) (1443:1443:1443))
+ (PORT datad (1444:1444:1444) (1444:1444:1444))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_7\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (650:650:650) (650:650:650))
+ (PORT datab (643:643:643) (643:643:643))
+ (PORT datac (685:685:685) (685:685:685))
+ (PORT datad (672:672:672) (672:672:672))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_6\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (638:638:638) (638:638:638))
+ (PORT datab (683:683:683) (683:683:683))
+ (PORT datac (651:651:651) (651:651:651))
+ (PORT datad (608:608:608) (608:608:608))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un14_vsync_counter_8\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (351:351:351) (351:351:351))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (375:375:375) (375:375:375))
+ (PORT datab (701:701:701) (701:701:701))
+ (PORT datac (1894:1894:1894) (1894:1894:1894))
+ (PORT datad (707:707:707) (707:707:707))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1984:1984:1984) (1984:1984:1984))
+ (PORT sclr (2780:2780:2780) (2780:2780:2780))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2476:2476:2476) (2476:2476:2476))
+ (PORT ena (1087:1087:1087) (1087:1087:1087))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (938:938:938) (938:938:938))
+ (PORT datac (461:461:461) (461:461:461))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1153:1153:1153) (1153:1153:1153))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2472:2472:2472) (2472:2472:2472))
+ (PORT ena (1819:1819:1819) (1819:1819:1819))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_next_1_sqmuxa_1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (936:936:936) (936:936:936))
+ (PORT datab (1161:1161:1161) (1161:1161:1161))
+ (PORT datac (716:716:716) (716:716:716))
+ (PORT datad (361:361:361) (361:361:361))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (604:604:604) (604:604:604))
+ (PORT datab (601:601:601) (601:601:601))
+ (PORT datac (622:622:622) (622:622:622))
+ (PORT datad (593:593:593) (593:593:593))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (921:921:921) (921:921:921))
+ (PORT datac (993:993:993) (993:993:993))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (635:635:635) (635:635:635))
+ (PORT datab (680:680:680) (680:680:680))
+ (PORT datac (650:650:650) (650:650:650))
+ (PORT datad (703:703:703) (703:703:703))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (621:621:621) (621:621:621))
+ (PORT datac (716:716:716) (716:716:716))
+ (PORT datad (356:356:356) (356:356:356))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_next_1_sqmuxa_2_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (352:352:352) (352:352:352))
+ (PORT datac (1248:1248:1248) (1248:1248:1248))
+ (PORT datad (358:358:358) (358:358:358))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_vsync_state_next_1_sqmuxa_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (359:359:359) (359:359:359))
+ (PORT datab (1225:1225:1225) (1225:1225:1225))
+ (PORT datac (1016:1016:1016) (1016:1016:1016))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_next_2_sqmuxa_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1276:1276:1276) (1276:1276:1276))
+ (PORT datab (350:350:350) (350:350:350))
+ (PORT datac (365:365:365) (365:365:365))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1221:1221:1221) (1221:1221:1221))
+ (PORT datab (1074:1074:1074) (1074:1074:1074))
+ (PORT datac (1273:1273:1273) (1273:1273:1273))
+ (PORT datad (1486:1486:1486) (1486:1486:1486))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1153:1153:1153) (1153:1153:1153))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2472:2472:2472) (2472:2472:2472))
+ (PORT ena (1819:1819:1819) (1819:1819:1819))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_3_iv_0_0__g0_0_a3_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (447:447:447) (447:447:447))
+ (PORT datac (1113:1113:1113) (1113:1113:1113))
+ (PORT datad (1452:1452:1452) (1452:1452:1452))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (369:369:369) (369:369:369))
+ (PORT datab (427:427:427) (427:427:427))
+ (PORT datac (540:540:540) (540:540:540))
+ (PORT datad (1087:1087:1087) (1087:1087:1087))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2472:2472:2472) (2472:2472:2472))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|d_set_vsync_counter_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1442:1442:1442) (1442:1442:1442))
+ (PORT datad (1447:1447:1447) (1447:1447:1447))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_next_1_sqmuxa_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (960:960:960) (960:960:960))
+ (PORT datab (620:620:620) (620:620:620))
+ (PORT datac (5539:5539:5539) (5539:5539:5539))
+ (PORT datad (1116:1116:1116) (1116:1116:1116))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1244:1244:1244) (1244:1244:1244))
+ (PORT datad (432:432:432) (432:432:432))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_9_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1470:1470:1470) (1470:1470:1470))
+ (PORT datac (1334:1334:1334) (1334:1334:1334))
+ (PORT sclr (1340:1340:1340) (1340:1340:1340))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2476:2476:2476) (2476:2476:2476))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1224:1224:1224) (1224:1224:1224))
+ (PORT datab (1075:1075:1075) (1075:1075:1075))
+ (PORT datac (446:446:446) (446:446:446))
+ (PORT datad (1486:1486:1486) (1486:1486:1486))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1153:1153:1153) (1153:1153:1153))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2472:2472:2472) (2472:2472:2472))
+ (PORT ena (1819:1819:1819) (1819:1819:1819))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (2096:2096:2096) (2096:2096:2096))
+ (PORT datab (1759:1759:1759) (1759:1759:1759))
+ (PORT datac (2102:2102:2102) (2102:2102:2102))
+ (PORT datad (1926:1926:1926) (1926:1926:1926))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2406:2406:2406) (2406:2406:2406))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_next_0_sqmuxa_1_1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (473:473:473) (473:473:473))
+ (PORT datab (5529:5529:5529) (5529:5529:5529))
+ (PORT datac (994:994:994) (994:994:994))
+ (PORT datad (1840:1840:1840) (1840:1840:1840))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (373:373:373) (373:373:373))
+ (PORT datad (938:938:938) (938:938:938))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2663:2663:2663) (2663:2663:2663))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2446:2446:2446) (2446:2446:2446))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_a_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (894:894:894) (894:894:894))
+ (PORT datab (1930:1930:1930) (1930:1930:1930))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (723:723:723) (723:723:723))
+ (PORT datab (686:686:686) (686:686:686))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (375:375:375) (375:375:375))
+ (PORT datad (546:546:546) (546:546:546))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2826:2826:2826) (2826:2826:2826))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2446:2446:2446) (2446:2446:2446))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (986:986:986) (986:986:986))
+ (PORT datab (927:927:927) (927:927:927))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (375:375:375) (375:375:375))
+ (PORT datad (814:814:814) (814:814:814))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2826:2826:2826) (2826:2826:2826))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2446:2446:2446) (2446:2446:2446))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (954:954:954) (954:954:954))
+ (PORT datab (421:421:421) (421:421:421))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (370:370:370) (370:370:370))
+ (PORT datad (939:939:939) (939:939:939))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2663:2663:2663) (2663:2663:2663))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2446:2446:2446) (2446:2446:2446))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (938:938:938) (938:938:938))
+ (PORT datab (694:694:694) (694:694:694))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (375:375:375) (375:375:375))
+ (PORT datad (545:545:545) (545:545:545))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2826:2826:2826) (2826:2826:2826))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2446:2446:2446) (2446:2446:2446))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datab (1009:1009:1009) (1009:1009:1009))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (949:949:949) (949:949:949))
+ (PORT datad (348:348:348) (348:348:348))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2663:2663:2663) (2663:2663:2663))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2446:2446:2446) (2446:2446:2446))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (991:991:991) (991:991:991))
+ (PORT datab (755:755:755) (755:755:755))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (2118:2118:2118) (2118:2118:2118))
+ (PORT datac (570:570:570) (570:570:570))
+ (PORT datad (542:542:542) (542:542:542))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2446:2446:2446) (2446:2446:2446))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglt4_2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (697:697:697) (697:697:697))
+ (PORT datac (667:667:667) (667:667:667))
+ (PORT datad (677:677:677) (677:677:677))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto5\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (721:721:721) (721:721:721))
+ (PORT datab (755:755:755) (755:755:755))
+ (PORT datac (972:972:972) (972:972:972))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datab (421:421:421) (421:421:421))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (948:948:948) (948:948:948))
+ (PORT datad (347:347:347) (347:347:347))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_8_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2663:2663:2663) (2663:2663:2663))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2446:2446:2446) (2446:2446:2446))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto8\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (972:972:972) (972:972:972))
+ (PORT datab (530:530:530) (530:530:530))
+ (PORT datac (905:905:905) (905:905:905))
+ (PORT datad (983:983:983) (983:983:983))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datad (962:962:962) (962:962:962))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (951:951:951) (951:951:951))
+ (PORT datad (569:569:569) (569:569:569))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_7_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2663:2663:2663) (2663:2663:2663))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2446:2446:2446) (2446:2446:2446))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un17_v_enablelt2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (719:719:719) (719:719:719))
+ (PORT datab (696:696:696) (696:696:696))
+ (PORT datad (679:679:679) (679:679:679))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un17_v_enablelto5\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1045:1045:1045) (1045:1045:1045))
+ (PORT datab (650:650:650) (650:650:650))
+ (PORT datac (714:714:714) (714:714:714))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un17_v_enablelto7\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (2205:2205:2205) (2205:2205:2205))
+ (PORT datac (1551:1551:1551) (1551:1551:1551))
+ (PORT datad (1612:1612:1612) (1612:1612:1612))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (441:441:441) (441:441:441))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1158:1158:1158) (1158:1158:1158))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (607:607:607) (607:607:607))
+ (PORT datab (423:423:423) (423:423:423))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (989:989:989) (989:989:989))
+ (PORT datab (419:419:419) (419:419:419))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|un2_toggle_counter_next_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (612:612:612) (612:612:612))
+ (PORT datab (925:925:925) (925:925:925))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (671:671:671) (671:671:671))
+ (PORT datab (927:927:927) (927:927:927))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (444:444:444) (444:444:444))
+ (PORT datab (972:972:972) (972:972:972))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (444:444:444) (444:444:444))
+ (PORT datab (929:929:929) (929:929:929))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datab (921:921:921) (921:921:921))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datab (949:949:949) (949:949:949))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_7_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datab (962:962:962) (962:962:962))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH datab cout (460:460:460) (460:460:460))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_9_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datab (912:912:912) (912:912:912))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH datab cout (460:460:460) (460:460:460))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_8_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_10_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (630:630:630) (630:630:630))
+ (PORT datab (915:915:915) (915:915:915))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_10_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_11_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (949:949:949) (949:949:949))
+ (PORT datab (420:420:420) (420:420:420))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_11_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_13_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (956:956:956) (956:956:956))
+ (PORT datab (422:422:422) (422:422:422))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_13_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_12_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (629:629:629) (629:629:629))
+ (PORT datab (900:900:900) (900:900:900))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_12_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_15_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datab (936:936:936) (936:936:936))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_15_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_14_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datab (938:938:938) (938:938:938))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_14_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_17_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datab (935:935:935) (935:935:935))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_17_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_16_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datab (942:942:942) (942:942:942))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_16_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_18_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datad (418:418:418) (418:418:418))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_18_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_19_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (955:955:955) (955:955:955))
+ (PORT datad (432:432:432) (432:432:432))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_19_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1326:1326:1326) (1326:1326:1326))
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto19_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (947:947:947) (947:947:947))
+ (PORT datab (629:629:629) (629:629:629))
+ (PORT datac (629:629:629) (629:629:629))
+ (PORT datad (609:609:609) (609:609:609))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto19_5\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (647:647:647) (647:647:647))
+ (PORT datab (604:604:604) (604:604:604))
+ (PORT datac (660:660:660) (660:660:660))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto7_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (645:645:645) (645:645:645))
+ (PORT datab (621:621:621) (621:621:621))
+ (PORT datac (614:614:614) (614:614:614))
+ (PORT datad (647:647:647) (647:647:647))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto7\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (679:679:679) (679:679:679))
+ (PORT datab (661:661:661) (661:661:661))
+ (PORT datac (367:367:367) (367:367:367))
+ (PORT datad (631:631:631) (631:631:631))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto10\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (641:641:641) (641:641:641))
+ (PORT datab (653:653:653) (653:653:653))
+ (PORT datac (629:629:629) (629:629:629))
+ (PORT datad (340:340:340) (340:340:340))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto19\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (644:644:644) (644:644:644))
+ (PORT datab (616:616:616) (616:616:616))
+ (PORT datac (368:368:368) (368:368:368))
+ (PORT datad (357:357:357) (357:357:357))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_sig_0_0_0_g1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_sig_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (370:370:370) (370:370:370))
+ (PORT datad (434:434:434) (434:434:434))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_sig_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (4675:4675:4675) (4675:4675:4675))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un9_v_enablelto6\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1135:1135:1135) (1135:1135:1135))
+ (PORT datab (444:444:444) (444:444:444))
+ (PORT datac (375:375:375) (375:375:375))
+ (PORT datad (454:454:454) (454:454:454))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un9_v_enablelto9\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (553:553:553) (553:553:553))
+ (PORT datab (952:952:952) (952:952:952))
+ (PORT datac (996:996:996) (996:996:996))
+ (PORT datad (1068:1068:1068) (1068:1068:1068))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (2016:2016:2016) (2016:2016:2016))
+ (PORT datac (2131:2131:2131) (2131:2131:2131))
+ (PORT datad (2080:2080:2080) (2080:2080:2080))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|h_enable_sig_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (439:439:439) (439:439:439))
+ (PORT datad (2077:2077:2077) (2077:2077:2077))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|h_enable_sig_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2904:2904:2904) (2904:2904:2904))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2406:2406:2406) (2406:2406:2406))
+ (PORT ena (1088:1088:1088) (1088:1088:1088))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|v_enable_sig_1_0_0_0_g0_i_o4_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1777:1777:1777) (1777:1777:1777))
+ (PORT datac (1224:1224:1224) (1224:1224:1224))
+ (PORT datad (1624:1624:1624) (1624:1624:1624))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|v_enable_sig_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1718:1718:1718) (1718:1718:1718))
+ (PORT datad (2112:2112:2112) (2112:2112:2112))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|v_enable_sig_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1997:1997:1997) (1997:1997:1997))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2469:2469:2469) (2469:2469:2469))
+ (PORT ena (1082:1082:1082) (1082:1082:1082))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|b_next_0_g0_3_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1933:1933:1933) (1933:1933:1933))
+ (PORT datab (952:952:952) (952:952:952))
+ (PORT datac (1000:1000:1000) (1000:1000:1000))
+ (PORT datad (2219:2219:2219) (2219:2219:2219))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|b_next_0_g0_5_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1995:1995:1995) (1995:1995:1995))
+ (PORT datab (339:339:339) (339:339:339))
+ (PORT datac (439:439:439) (439:439:439))
+ (PORT datad (347:347:347) (347:347:347))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un13_v_enablelto8_a\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (720:720:720) (720:720:720))
+ (PORT datab (649:649:649) (649:649:649))
+ (PORT datac (715:715:715) (715:715:715))
+ (PORT datad (768:768:768) (768:768:768))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un13_v_enablelto8\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (2236:2236:2236) (2236:2236:2236))
+ (PORT datab (1601:1601:1601) (1601:1601:1601))
+ (PORT datac (2226:2226:2226) (2226:2226:2226))
+ (PORT datad (2112:2112:2112) (2112:2112:2112))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|b_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (552:552:552) (552:552:552))
+ (PORT datab (530:530:530) (530:530:530))
+ (PORT datac (542:542:542) (542:542:542))
+ (PORT datad (535:535:535) (535:535:535))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|b_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (4775:4775:4775) (4775:4775:4775))
+ (PORT clk (2406:2406:2406) (2406:2406:2406))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_hsync_state_3_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1769:1769:1769) (1769:1769:1769))
+ (PORT datad (2108:2108:2108) (2108:2108:2108))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|h_sync_1_0_0_0_g1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1824:1824:1824) (1824:1824:1824))
+ (PORT datab (414:414:414) (414:414:414))
+ (PORT datac (360:360:360) (360:360:360))
+ (PORT datad (712:712:712) (712:712:712))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|h_sync_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (475:475:475) (475:475:475))
+ (PORT datab (971:971:971) (971:971:971))
+ (PORT datac (5522:5522:5522) (5522:5522:5522))
+ (PORT datad (361:361:361) (361:361:361))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|h_sync_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2472:2472:2472) (2472:2472:2472))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_vsync_state_2_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1276:1276:1276) (1276:1276:1276))
+ (PORT datac (1918:1918:1918) (1918:1918:1918))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|v_sync_1_0_0_0_g1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (367:367:367) (367:367:367))
+ (PORT datab (446:446:446) (446:446:446))
+ (PORT datac (456:456:456) (456:456:456))
+ (PORT datad (454:454:454) (454:454:454))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|v_sync_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (361:361:361) (361:361:361))
+ (PORT datab (454:454:454) (454:454:454))
+ (PORT datac (649:649:649) (649:649:649))
+ (PORT datad (5532:5532:5532) (5532:5532:5532))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|v_sync_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2472:2472:2472) (2472:2472:2472))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE r0_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3105:3105:3105) (3105:3105:3105))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE r1_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3154:3154:3154) (3154:3154:3154))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE r2_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2738:2738:2738) (2738:2738:2738))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE g0_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2818:2818:2818) (2818:2818:2818))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE g1_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2483:2483:2483) (2483:2483:2483))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE g2_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2690:2690:2690) (2690:2690:2690))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE b0_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2940:2940:2940) (2940:2940:2940))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE b1_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3041:3041:3041) (3041:3041:3041))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE hsync_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3330:3330:3330) (3330:3330:3330))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE vsync_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3711:3711:3711) (3711:3711:3711))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3021:3021:3021) (3021:3021:3021))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2553:2553:2553) (2553:2553:2553))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3478:3478:3478) (3478:3478:3478))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2818:2818:2818) (2818:2818:2818))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2852:2852:2852) (2852:2852:2852))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3154:3154:3154) (3154:3154:3154))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2852:2852:2852) (2852:2852:2852))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3403:3403:3403) (3403:3403:3403))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3478:3478:3478) (3478:3478:3478))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_9_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2480:2480:2480) (2480:2480:2480))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_10_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3403:3403:3403) (3403:3403:3403))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_11_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2611:2611:2611) (2611:2611:2611))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_12_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2574:2574:2574) (2574:2574:2574))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_13_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2652:2652:2652) (2652:2652:2652))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_hsync_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2346:2346:2346) (2346:2346:2346))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_vsync_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3030:3030:3030) (3030:3030:3030))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3136:3136:3136) (3136:3136:3136))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3114:3114:3114) (3114:3114:3114))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2878:2878:2878) (2878:2878:2878))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2475:2475:2475) (2475:2475:2475))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2800:2800:2800) (2800:2800:2800))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2501:2501:2501) (2501:2501:2501))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2569:2569:2569) (2569:2569:2569))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3597:3597:3597) (3597:3597:3597))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3102:3102:3102) (3102:3102:3102))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_9_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2816:2816:2816) (2816:2816:2816))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1913:1913:1913) (1913:1913:1913))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2122:2122:2122) (2122:2122:2122))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2616:2616:2616) (2616:2616:2616))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2087:2087:2087) (2087:2087:2087))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3061:3061:3061) (3061:3061:3061))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3096:3096:3096) (3096:3096:3096))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2323:2323:2323) (2323:2323:2323))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3195:3195:3195) (3195:3195:3195))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2104:2104:2104) (2104:2104:2104))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_set_column_counter_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2342:2342:2342) (2342:2342:2342))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_set_line_counter_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3321:3321:3321) (3321:3321:3321))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1781:1781:1781) (1781:1781:1781))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1547:1547:1547) (1547:1547:1547))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2472:2472:2472) (2472:2472:2472))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2240:2240:2240) (2240:2240:2240))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3471:3471:3471) (3471:3471:3471))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2016:2016:2016) (2016:2016:2016))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1811:1811:1811) (1811:1811:1811))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2193:2193:2193) (2193:2193:2193))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2750:2750:2750) (2750:2750:2750))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_9_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2028:2028:2028) (2028:2028:2028))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2610:2610:2610) (2610:2610:2610))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2795:2795:2795) (2795:2795:2795))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2695:2695:2695) (2695:2695:2695))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2754:2754:2754) (2754:2754:2754))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2836:2836:2836) (2836:2836:2836))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3493:3493:3493) (3493:3493:3493))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2039:2039:2039) (2039:2039:2039))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2624:2624:2624) (2624:2624:2624))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2811:2811:2811) (2811:2811:2811))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_9_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2804:2804:2804) (2804:2804:2804))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_set_hsync_counter_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3114:3114:3114) (3114:3114:3114))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_set_vsync_counter_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3239:3239:3239) (3239:3239:3239))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_h_enable_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2843:2843:2843) (2843:2843:2843))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_v_enable_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2052:2052:2052) (2052:2052:2052))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_r_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2483:2483:2483) (2483:2483:2483))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_g_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3568:3568:3568) (3568:3568:3568))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_b_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2940:2940:2940) (2940:2940:2940))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2378:2378:2378) (2378:2378:2378))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4501:4501:4501) (4501:4501:4501))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3999:3999:3999) (3999:3999:3999))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2214:2214:2214) (2214:2214:2214))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2501:2501:2501) (2501:2501:2501))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2474:2474:2474) (2474:2474:2474))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2066:2066:2066) (2066:2066:2066))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2805:2805:2805) (2805:2805:2805))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2996:2996:2996) (2996:2996:2996))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2527:2527:2527) (2527:2527:2527))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2287:2287:2287) (2287:2287:2287))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2516:2516:2516) (2516:2516:2516))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3341:3341:3341) (3341:3341:3341))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2287:2287:2287) (2287:2287:2287))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_state_clk_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2588:2588:2588) (2588:2588:2588))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_toggle_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1797:1797:1797) (1797:1797:1797))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2249:2249:2249) (2249:2249:2249))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2567:2567:2567) (2567:2567:2567))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2338:2338:2338) (2338:2338:2338))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3299:3299:3299) (3299:3299:3299))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2107:2107:2107) (2107:2107:2107))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2826:2826:2826) (2826:2826:2826))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2476:2476:2476) (2476:2476:2476))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3158:3158:3158) (3158:3158:3158))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2332:2332:2332) (2332:2332:2332))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_9_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2603:2603:2603) (2603:2603:2603))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_10_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1851:1851:1851) (1851:1851:1851))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_11_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2358:2358:2358) (2358:2358:2358))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_12_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1787:1787:1787) (1787:1787:1787))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_13_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2059:2059:2059) (2059:2059:2059))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_14_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2707:2707:2707) (2707:2707:2707))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_15_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3500:3500:3500) (3500:3500:3500))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_16_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3058:3058:3058) (3058:3058:3058))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_17_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1848:1848:1848) (1848:1848:1848))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_18_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2070:2070:2070) (2070:2070:2070))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_19_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3453:3453:3453) (3453:3453:3453))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_20_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2624:2624:2624) (2624:2624:2624))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_21_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2151:2151:2151) (2151:2151:2151))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_22_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2787:2787:2787) (2787:2787:2787))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_23_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3003:3003:3003) (3003:3003:3003))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_24_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3139:3139:3139) (3139:3139:3139))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+)
projects / dide_16.git / blobdiff