after slot5

[dide_16.git] / bsp4 / Designflow / ppr / sim / db / vga.tmw_info

diff --git a/bsp4/Designflow/ppr/sim/db/vga.tmw_info b/bsp4/Designflow/ppr/sim/db/vga.tmw_info
new file mode 100644 (file)
index 0000000..4526cc2
--- /dev/null
+++ b/bsp4/Designflow/ppr/sim/db/vga.tmw_info
@@ -0,0 +1,7 @@
+start_full_compilation:s:00:01:19
+start_analysis_synthesis:s:00:00:13-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:36-start_full_compilation
+start_assembler:s:00:00:23-start_full_compilation
+start_timing_analyzer:s:00:00:03-start_full_compilation
+start_eda_netlist_writer:s:00:00:04-start_full_compilation