--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 3 17:31:35 2009 " "Info: Processing started: Tue Nov 3 17:31:35 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_pin " "Info: Assuming node \"clk_pin\" is an undefined clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 4476 16 0 } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "clk_pin" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_pin register vga_driver:vga_driver_unit\|hsync_state_0 register vga_driver:vga_driver_unit\|line_counter_sig_2 182.42 MHz 5.482 ns Internal " "Info: Clock \"clk_pin\" has Internal fmax of 182.42 MHz between source register \"vga_driver:vga_driver_unit\|hsync_state_0\" and destination register \"vga_driver:vga_driver_unit\|line_counter_sig_2\" (period= 5.482 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.270 ns + Longest register register " "Info: + Longest register to register delay is 5.270 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_driver:vga_driver_unit\|hsync_state_0 1 REG LC_X18_Y22_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y22_N2; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.275 ns) + CELL(0.087 ns) 1.362 ns vga_driver:vga_driver_unit\|d_set_hsync_counter 2 COMB LC_X18_Y26_N6 10 " "Info: 2: + IC(1.275 ns) + CELL(0.087 ns) = 1.362 ns; Loc. = LC_X18_Y26_N6; Fanout = 10; COMB Node = 'vga_driver:vga_driver_unit\|d_set_hsync_counter'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.362 ns" { vga_driver:vga_driver_unit|hsync_state_0 vga_driver:vga_driver_unit|d_set_hsync_counter } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 156 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.959 ns) + CELL(0.451 ns) 3.772 ns vga_driver:vga_driver_unit\|un1_line_counter_sig_cout\[1\]~COUT1_9 3 COMB LC_X35_Y18_N5 2 " "Info: 3: + IC(1.959 ns) + CELL(0.451 ns) = 3.772 ns; Loc. = LC_X35_Y18_N5; Fanout = 2; COMB Node = 'vga_driver:vga_driver_unit\|un1_line_counter_sig_cout\[1\]~COUT1_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.410 ns" { vga_driver:vga_driver_unit|d_set_hsync_counter vga_driver:vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 227 38 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 4.221 ns vga_driver:vga_driver_unit\|un1_line_counter_sig_combout\[3\] 4 COMB LC_X35_Y18_N6 1 " "Info: 4: + IC(0.000 ns) + CELL(0.449 ns) = 4.221 ns; Loc. = LC_X35_Y18_N6; Fanout = 1; COMB Node = 'vga_driver:vga_driver_unit\|un1_line_counter_sig_combout\[3\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.449 ns" { vga_driver:vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 vga_driver:vga_driver_unit|un1_line_counter_sig_combout[3] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 226 41 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.814 ns) + CELL(0.235 ns) 5.270 ns vga_driver:vga_driver_unit\|line_counter_sig_2 5 REG LC_X33_Y18_N5 9 " "Info: 5: + IC(0.814 ns) + CELL(0.235 ns) = 5.270 ns; Loc. = LC_X33_Y18_N5; Fanout = 9; REG Node = 'vga_driver:vga_driver_unit\|line_counter_sig_2'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.049 ns" { vga_driver:vga_driver_unit|un1_line_counter_sig_combout[3] vga_driver:vga_driver_unit|line_counter_sig_2 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 95 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns ( 23.19 % ) " "Info: Total cell delay = 1.222 ns ( 23.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.048 ns ( 76.81 % ) " "Info: Total interconnect delay = 4.048 ns ( 76.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.270 ns" { vga_driver:vga_driver_unit|hsync_state_0 vga_driver:vga_driver_unit|d_set_hsync_counter vga_driver:vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 vga_driver:vga_driver_unit|un1_line_counter_sig_combout[3] vga_driver:vga_driver_unit|line_counter_sig_2 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "5.270 ns" { vga_driver:vga_driver_unit|hsync_state_0 {} vga_driver:vga_driver_unit|d_set_hsync_counter {} vga_driver:vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 {} vga_driver:vga_driver_unit|un1_line_counter_sig_combout[3] {} vga_driver:vga_driver_unit|line_counter_sig_2 {} } { 0.000ns 1.275ns 1.959ns 0.000ns 0.814ns } { 0.000ns 0.087ns 0.451ns 0.449ns 0.235ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.026 ns - Smallest " "Info: - Smallest clock skew is -0.026 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.314 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_pin\" to destination register is 3.314 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 82 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 82; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 4476 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.886 ns) + CELL(0.560 ns) 3.314 ns vga_driver:vga_driver_unit\|line_counter_sig_2 2 REG LC_X33_Y18_N5 9 " "Info: 2: + IC(1.886 ns) + CELL(0.560 ns) = 3.314 ns; Loc. = LC_X33_Y18_N5; Fanout = 9; REG Node = 'vga_driver:vga_driver_unit\|line_counter_sig_2'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.446 ns" { clk_pin vga_driver:vga_driver_unit|line_counter_sig_2 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 95 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 43.09 % ) " "Info: Total cell delay = 1.428 ns ( 43.09 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.886 ns ( 56.91 % ) " "Info: Total interconnect delay = 1.886 ns ( 56.91 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.314 ns" { clk_pin vga_driver:vga_driver_unit|line_counter_sig_2 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.314 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|line_counter_sig_2 {} } { 0.000ns 0.000ns 1.886ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin source 3.340 ns - Longest register " "Info: - Longest clock path from clock \"clk_pin\" to source register is 3.340 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 82 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 82; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 4476 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.912 ns) + CELL(0.560 ns) 3.340 ns vga_driver:vga_driver_unit\|hsync_state_0 2 REG LC_X18_Y22_N2 4 " "Info: 2: + IC(1.912 ns) + CELL(0.560 ns) = 3.340 ns; Loc. = LC_X18_Y22_N2; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.472 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 42.75 % ) " "Info: Total cell delay = 1.428 ns ( 42.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.912 ns ( 57.25 % ) " "Info: Total interconnect delay = 1.912 ns ( 57.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.340 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.340 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 0.000ns 1.912ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.314 ns" { clk_pin vga_driver:vga_driver_unit|line_counter_sig_2 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.314 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|line_counter_sig_2 {} } { 0.000ns 0.000ns 1.886ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.340 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.340 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 0.000ns 1.912ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 95 28 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.270 ns" { vga_driver:vga_driver_unit|hsync_state_0 vga_driver:vga_driver_unit|d_set_hsync_counter vga_driver:vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 vga_driver:vga_driver_unit|un1_line_counter_sig_combout[3] vga_driver:vga_driver_unit|line_counter_sig_2 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "5.270 ns" { vga_driver:vga_driver_unit|hsync_state_0 {} vga_driver:vga_driver_unit|d_set_hsync_counter {} vga_driver:vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 {} vga_driver:vga_driver_unit|un1_line_counter_sig_combout[3] {} vga_driver:vga_driver_unit|line_counter_sig_2 {} } { 0.000ns 1.275ns 1.959ns 0.000ns 0.814ns } { 0.000ns 0.087ns 0.451ns 0.449ns 0.235ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.314 ns" { clk_pin vga_driver:vga_driver_unit|line_counter_sig_2 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.314 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|line_counter_sig_2 {} } { 0.000ns 0.000ns 1.886ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.340 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.340 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 0.000ns 1.912ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "vga_driver:vga_driver_unit\|hsync_state_2 reset_pin clk_pin 7.334 ns register " "Info: tsu for register \"vga_driver:vga_driver_unit\|hsync_state_2\" (data pin = \"reset_pin\", clock pin = \"clk_pin\") is 7.334 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.664 ns + Longest pin register " "Info: + Longest pin to register delay is 10.664 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns reset_pin 1 PIN PIN_P24 10 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_P24; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 4477 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.528 ns) + CELL(0.087 ns) 6.483 ns vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X17_Y22_N4 51 " "Info: 2: + IC(5.528 ns) + CELL(0.087 ns) = 6.483 ns; Loc. = LC_X17_Y22_N4; Fanout = 51; COMB Node = 'vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.615 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 155 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.806 ns) + CELL(0.459 ns) 8.748 ns vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0 3 COMB LC_X17_Y14_N7 6 " "Info: 3: + IC(1.806 ns) + CELL(0.459 ns) = 8.748 ns; Loc. = LC_X17_Y14_N7; Fanout = 6; COMB Node = 'vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.265 ns" { vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 249 33 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.190 ns) + CELL(0.726 ns) 10.664 ns vga_driver:vga_driver_unit\|hsync_state_2 4 REG LC_X18_Y22_N1 4 " "Info: 4: + IC(1.190 ns) + CELL(0.726 ns) = 10.664 ns; Loc. = LC_X18_Y22_N1; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_2'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.916 ns" { vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_2 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.140 ns ( 20.07 % ) " "Info: Total cell delay = 2.140 ns ( 20.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.524 ns ( 79.93 % ) " "Info: Total interconnect delay = 8.524 ns ( 79.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "10.664 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_2 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "10.664 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga_driver:vga_driver_unit|hsync_state_2 {} } { 0.000ns 0.000ns 5.528ns 1.806ns 1.190ns } { 0.000ns 0.868ns 0.087ns 0.459ns 0.726ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 111 23 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.340 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_pin\" to destination register is 3.340 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 82 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 82; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 4476 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.912 ns) + CELL(0.560 ns) 3.340 ns vga_driver:vga_driver_unit\|hsync_state_2 2 REG LC_X18_Y22_N1 4 " "Info: 2: + IC(1.912 ns) + CELL(0.560 ns) = 3.340 ns; Loc. = LC_X18_Y22_N1; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_2'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.472 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_2 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 42.75 % ) " "Info: Total cell delay = 1.428 ns ( 42.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.912 ns ( 57.25 % ) " "Info: Total interconnect delay = 1.912 ns ( 57.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.340 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_2 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.340 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_2 {} } { 0.000ns 0.000ns 1.912ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "10.664 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_2 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "10.664 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga_driver:vga_driver_unit|hsync_state_2 {} } { 0.000ns 0.000ns 5.528ns 1.806ns 1.190ns } { 0.000ns 0.868ns 0.087ns 0.459ns 0.726ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.340 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_2 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.340 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_2 {} } { 0.000ns 0.000ns 1.912ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "clk_pin d_set_vsync_counter vga_driver:vga_driver_unit\|vsync_state_0 10.905 ns register " "Info: tco from clock \"clk_pin\" to destination pin \"d_set_vsync_counter\" through register \"vga_driver:vga_driver_unit\|vsync_state_0\" is 10.905 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin source 3.340 ns + Longest register " "Info: + Longest clock path from clock \"clk_pin\" to source register is 3.340 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 82 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 82; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 4476 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.912 ns) + CELL(0.560 ns) 3.340 ns vga_driver:vga_driver_unit\|vsync_state_0 2 REG LC_X17_Y22_N5 5 " "Info: 2: + IC(1.912 ns) + CELL(0.560 ns) = 3.340 ns; Loc. = LC_X17_Y22_N5; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit\|vsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.472 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 110 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 42.75 % ) " "Info: Total cell delay = 1.428 ns ( 42.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.912 ns ( 57.25 % ) " "Info: Total interconnect delay = 1.912 ns ( 57.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.340 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.340 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_0 {} } { 0.000ns 0.000ns 1.912ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 110 23 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.389 ns + Longest register pin " "Info: + Longest register to pin delay is 7.389 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_driver:vga_driver_unit\|vsync_state_0 1 REG LC_X17_Y22_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y22_N5; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit\|vsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga_driver:vga_driver_unit|vsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 110 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.442 ns) + CELL(0.213 ns) 1.655 ns vga_driver:vga_driver_unit\|d_set_vsync_counter 2 COMB LC_X19_Y24_N5 2 " "Info: 2: + IC(1.442 ns) + CELL(0.213 ns) = 1.655 ns; Loc. = LC_X19_Y24_N5; Fanout = 2; COMB Node = 'vga_driver:vga_driver_unit\|d_set_vsync_counter'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.655 ns" { vga_driver:vga_driver_unit|vsync_state_0 vga_driver:vga_driver_unit|d_set_vsync_counter } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 148 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.239 ns) + CELL(2.495 ns) 7.389 ns d_set_vsync_counter 3 PIN PIN_L23 0 " "Info: 3: + IC(3.239 ns) + CELL(2.495 ns) = 7.389 ns; Loc. = PIN_L23; Fanout = 0; PIN Node = 'd_set_vsync_counter'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.734 ns" { vga_driver:vga_driver_unit|d_set_vsync_counter d_set_vsync_counter } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 4498 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.708 ns ( 36.65 % ) " "Info: Total cell delay = 2.708 ns ( 36.65 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.681 ns ( 63.35 % ) " "Info: Total interconnect delay = 4.681 ns ( 63.35 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.389 ns" { vga_driver:vga_driver_unit|vsync_state_0 vga_driver:vga_driver_unit|d_set_vsync_counter d_set_vsync_counter } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.389 ns" { vga_driver:vga_driver_unit|vsync_state_0 {} vga_driver:vga_driver_unit|d_set_vsync_counter {} d_set_vsync_counter {} } { 0.000ns 1.442ns 3.239ns } { 0.000ns 0.213ns 2.495ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.340 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.340 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_0 {} } { 0.000ns 0.000ns 1.912ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.389 ns" { vga_driver:vga_driver_unit|vsync_state_0 vga_driver:vga_driver_unit|d_set_vsync_counter d_set_vsync_counter } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.389 ns" { vga_driver:vga_driver_unit|vsync_state_0 {} vga_driver:vga_driver_unit|d_set_vsync_counter {} d_set_vsync_counter {} } { 0.000ns 1.442ns 3.239ns } { 0.000ns 0.213ns 2.495ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "reset_pin seven_seg_pin\[8\] 12.465 ns Longest " "Info: Longest tpd from source pin \"reset_pin\" to destination pin \"seven_seg_pin\[8\]\" is 12.465 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns reset_pin 1 PIN PIN_P24 10 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_P24; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 4477 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.528 ns) + CELL(0.087 ns) 6.483 ns vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X17_Y22_N4 51 " "Info: 2: + IC(5.528 ns) + CELL(0.087 ns) = 6.483 ns; Loc. = LC_X17_Y22_N4; Fanout = 51; COMB Node = 'vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.615 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 155 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.478 ns) + CELL(2.504 ns) 12.465 ns seven_seg_pin\[8\] 3 PIN PIN_B10 0 " "Info: 3: + IC(3.478 ns) + CELL(2.504 ns) = 12.465 ns; Loc. = PIN_B10; Fanout = 0; PIN Node = 'seven_seg_pin\[8\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.982 ns" { vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[8] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 4488 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.459 ns ( 27.75 % ) " "Info: Total cell delay = 3.459 ns ( 27.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.006 ns ( 72.25 % ) " "Info: Total interconnect delay = 9.006 ns ( 72.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "12.465 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[8] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "12.465 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[8] {} } { 0.000ns 0.000ns 5.528ns 3.478ns } { 0.000ns 0.868ns 0.087ns 2.504ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "vga_driver:vga_driver_unit\|vsync_state_6 reset_pin clk_pin -3.191 ns register " "Info: th for register \"vga_driver:vga_driver_unit\|vsync_state_6\" (data pin = \"reset_pin\", clock pin = \"clk_pin\") is -3.191 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.340 ns + Longest register " "Info: + Longest clock path from clock \"clk_pin\" to destination register is 3.340 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 82 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 82; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 4476 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.912 ns) + CELL(0.560 ns) 3.340 ns vga_driver:vga_driver_unit\|vsync_state_6 2 REG LC_X17_Y22_N4 4 " "Info: 2: + IC(1.912 ns) + CELL(0.560 ns) = 3.340 ns; Loc. = LC_X17_Y22_N4; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit\|vsync_state_6'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.472 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_6 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 107 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 42.75 % ) " "Info: Total cell delay = 1.428 ns ( 42.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.912 ns ( 57.25 % ) " "Info: Total interconnect delay = 1.912 ns ( 57.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.340 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_6 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.340 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_6 {} } { 0.000ns 0.000ns 1.912ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 107 23 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.631 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.631 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns reset_pin 1 PIN PIN_P24 10 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_P24; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 4477 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.528 ns) + CELL(0.235 ns) 6.631 ns vga_driver:vga_driver_unit\|vsync_state_6 2 REG LC_X17_Y22_N4 4 " "Info: 2: + IC(5.528 ns) + CELL(0.235 ns) = 6.631 ns; Loc. = LC_X17_Y22_N4; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit\|vsync_state_6'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.763 ns" { reset_pin vga_driver:vga_driver_unit|vsync_state_6 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 107 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.103 ns ( 16.63 % ) " "Info: Total cell delay = 1.103 ns ( 16.63 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.528 ns ( 83.37 % ) " "Info: Total interconnect delay = 5.528 ns ( 83.37 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.631 ns" { reset_pin vga_driver:vga_driver_unit|vsync_state_6 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.631 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_6 {} } { 0.000ns 0.000ns 5.528ns } { 0.000ns 0.868ns 0.235ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.340 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_6 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.340 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_6 {} } { 0.000ns 0.000ns 1.912ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.631 ns" { reset_pin vga_driver:vga_driver_unit|vsync_state_6 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.631 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_6 {} } { 0.000ns 0.000ns 5.528ns } { 0.000ns 0.868ns 0.235ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Peak virtual memory: 141 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 3 17:31:36 2009 " "Info: Processing ended: Tue Nov 3 17:31:36 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
projects / dide_16.git / blobdiff