--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 3 17:30:30 2009 " "Info: Processing started: Tue Nov 3 17:30:30 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vga -c vga " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga -c vga" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../syn/rev_1/vga.vqm 3 3 " "Info: Found 3 design units, including 3 entities, in source file ../../syn/rev_1/vga.vqm" { { "Info" "ISGN_ENTITY_NAME" "1 vga_driver " "Info: Found entity 1: vga_driver" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 25 18 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 vga_control " "Info: Found entity 2: vga_control" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 3147 19 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 vga " "Info: Found entity 3: vga" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 4440 11 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "vga " "Info: Elaborating entity \"vga\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_driver vga_driver:vga_driver_unit " "Info: Elaborating entity \"vga_driver\" for hierarchy \"vga_driver:vga_driver_unit\"" { } { { "../../syn/rev_1/vga.vqm" "vga_driver_unit" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 6195 3 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_control vga_control:vga_control_unit " "Info: Elaborating entity \"vga_control\" for hierarchy \"vga_control:vga_control_unit\"" { } { { "../../syn/rev_1/vga.vqm" "vga_control_unit" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 6251 3 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "vga_control:vga_control_unit\|toggle_sig_0_0_0_g1 " "Info (17048): Logic cell \"vga_control:vga_control_unit\|toggle_sig_0_0_0_g1\"" { } { { "../../syn/rev_1/vga.vqm" "toggle_sig_0_0_0_g1_cZ" { Text "/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vqm" 4013 3 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Found the following redundant logic cells in design" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "292 " "Info: Implemented 292 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "115 " "Info: Implemented 115 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "175 " "Info: Implemented 175 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "185 " "Info: Peak virtual memory: 185 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 3 17:30:34 2009 " "Info: Processing ended: Tue Nov 3 17:30:34 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
projects / dide_16.git / blobdiff