after slot5

[dide_16.git] / bsp4 / Designflow / ppr / download / simulation / modelsim / vga_pll_v.sdo

diff --git a/bsp4/Designflow/ppr/download/simulation/modelsim/vga_pll_v.sdo b/bsp4/Designflow/ppr/download/simulation/modelsim/vga_pll_v.sdo
new file mode 100644 (file)
index 0000000..67e0696
--- /dev/null
+++ b/bsp4/Designflow/ppr/download/simulation/modelsim/vga_pll_v.sdo
@@ -0,0 +1,5561 @@
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP1S25F672C6 Package FBGA672
+// 
+
+// 
+// This SDF file should be used for ModelSim-Altera (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "vga_pll")
+  (DATE "11/03/2009 17:37:44")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II")
+  (VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE board_clk\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio combout (760:760:760) (760:760:760))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_pll")
+    (INSTANCE inst1\|altpll_component\|pll)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (649:649:649) (649:649:649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|reset_pin_in\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio combout (1141:1141:1141) (1141:1141:1141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|dly_counter_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (5257:5257:5257) (5257:5257:5257))
+        (PORT datac (1189:1189:1189) (1189:1189:1189))
+        (PORT datad (457:457:457) (457:457:457))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|dly_counter_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|dly_counter_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (4837:4837:4837) (4837:4837:4837))
+        (PORT datab (948:948:948) (948:948:948))
+        (PORT datad (1459:1459:1459) (1459:1459:1459))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|dly_counter_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2058:2058:2058) (2058:2058:2058))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (5264:5264:5264) (5264:5264:5264))
+        (PORT datac (1184:1184:1184) (1184:1184:1184))
+        (PORT datad (466:466:466) (466:466:466))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_6_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1294:1294:1294) (1294:1294:1294))
+        (PORT datad (1064:1064:1064) (1064:1064:1064))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH qfbkin combout (291:291:291) (291:291:291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_6_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1384:1384:1384) (1384:1384:1384))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2110:2110:2110) (2110:2110:2110))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+        (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (423:423:423) (423:423:423))
+        (PORT datac (1001:1001:1001) (1001:1001:1001))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1772:1772:1772) (1772:1772:1772))
+        (PORT datac (1091:1091:1091) (1091:1091:1091))
+        (PORT sclr (1307:1307:1307) (1307:1307:1307))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (419:419:419) (419:419:419))
+        (PORT datac (999:999:999) (999:999:999))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1772:1772:1772) (1772:1772:1772))
+        (PORT datac (1089:1089:1089) (1089:1089:1089))
+        (PORT sclr (1307:1307:1307) (1307:1307:1307))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (444:444:444) (444:444:444))
+        (PORT datac (998:998:998) (998:998:998))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_2_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1772:1772:1772) (1772:1772:1772))
+        (PORT datac (1088:1088:1088) (1088:1088:1088))
+        (PORT sclr (1307:1307:1307) (1307:1307:1307))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (437:437:437) (437:437:437))
+        (PORT datac (1001:1001:1001) (1001:1001:1001))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_3_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1772:1772:1772) (1772:1772:1772))
+        (PORT datac (1091:1091:1091) (1091:1091:1091))
+        (PORT sclr (1307:1307:1307) (1307:1307:1307))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_7.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (701:701:701) (701:701:701))
+        (PORT datab (602:602:602) (602:602:602))
+        (PORT datac (716:716:716) (716:716:716))
+        (PORT datad (643:643:643) (643:643:643))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datac (1004:1004:1004) (1004:1004:1004))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout (551:551:551) (551:551:551))
+        (IOPATH cin0 cout (135:135:135) (135:135:135))
+        (IOPATH cin1 cout (123:123:123) (123:123:123))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_4_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1772:1772:1772) (1772:1772:1772))
+        (PORT datac (1094:1094:1094) (1094:1094:1094))
+        (PORT sclr (1307:1307:1307) (1307:1307:1307))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (420:420:420) (420:420:420))
+        (PORT datac (1010:1010:1010) (1010:1010:1010))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_5_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1772:1772:1772) (1772:1772:1772))
+        (PORT datac (1100:1100:1100) (1100:1100:1100))
+        (PORT sclr (1307:1307:1307) (1307:1307:1307))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (422:422:422) (422:422:422))
+        (PORT datac (1009:1009:1009) (1009:1009:1009))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_6_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1772:1772:1772) (1772:1772:1772))
+        (PORT datac (1099:1099:1099) (1099:1099:1099))
+        (PORT sclr (1307:1307:1307) (1307:1307:1307))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_7_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (436:436:436) (436:436:436))
+        (PORT datac (1008:1008:1008) (1008:1008:1008))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_7_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1772:1772:1772) (1772:1772:1772))
+        (PORT datac (1098:1098:1098) (1098:1098:1098))
+        (PORT sclr (1307:1307:1307) (1307:1307:1307))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_8_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datac (1008:1008:1008) (1008:1008:1008))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_8_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1772:1772:1772) (1772:1772:1772))
+        (PORT datac (1098:1098:1098) (1098:1098:1098))
+        (PORT sclr (1307:1307:1307) (1307:1307:1307))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_9_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1006:1006:1006) (1006:1006:1006))
+        (PORT datad (432:432:432) (432:432:432))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_9_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1772:1772:1772) (1772:1772:1772))
+        (PORT datac (1096:1096:1096) (1096:1096:1096))
+        (PORT sclr (1307:1307:1307) (1307:1307:1307))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9_3.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (679:679:679) (679:679:679))
+        (PORT datab (611:611:611) (611:611:611))
+        (PORT datac (972:972:972) (972:972:972))
+        (PORT datad (699:699:699) (699:699:699))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (367:367:367) (367:367:367))
+        (PORT datab (668:668:668) (668:668:668))
+        (PORT datac (939:939:939) (939:939:939))
+        (PORT datad (253:253:253) (253:253:253))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|G_2.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1040:1040:1040) (1040:1040:1040))
+        (PORT datab (993:993:993) (993:993:993))
+        (PORT datac (374:374:374) (374:374:374))
+        (PORT datad (1028:1028:1028) (1028:1028:1028))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_2.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (681:681:681) (681:681:681))
+        (PORT datab (629:629:629) (629:629:629))
+        (PORT datac (689:689:689) (689:689:689))
+        (PORT datad (695:695:695) (695:695:695))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (700:700:700) (700:700:700))
+        (PORT datab (343:343:343) (343:343:343))
+        (PORT datac (376:376:376) (376:376:376))
+        (PORT datad (619:619:619) (619:619:619))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_3.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1239:1239:1239) (1239:1239:1239))
+        (PORT datab (1156:1156:1156) (1156:1156:1156))
+        (PORT datac (1173:1173:1173) (1173:1173:1173))
+        (PORT datad (1457:1457:1457) (1457:1457:1457))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_2.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1217:1217:1217) (1217:1217:1217))
+        (PORT datab (1182:1182:1182) (1182:1182:1182))
+        (PORT datac (1161:1161:1161) (1161:1161:1161))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_1.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1222:1222:1222) (1222:1222:1222))
+        (PORT datac (1137:1137:1137) (1137:1137:1137))
+        (PORT datad (1194:1194:1194) (1194:1194:1194))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_4.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1235:1235:1235) (1235:1235:1235))
+        (PORT datab (1381:1381:1381) (1381:1381:1381))
+        (PORT datac (1214:1214:1214) (1214:1214:1214))
+        (PORT datad (1456:1456:1456) (1456:1456:1456))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_3.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1187:1187:1187) (1187:1187:1187))
+        (PORT datac (1159:1159:1159) (1159:1159:1159))
+        (PORT datad (1164:1164:1164) (1164:1164:1164))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (682:682:682) (682:682:682))
+        (PORT datad (1229:1229:1229) (1229:1229:1229))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_5_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1786:1786:1786) (1786:1786:1786))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (PORT ena (1281:1281:1281) (1281:1281:1281))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (376:376:376) (376:376:376))
+        (PORT datab (351:351:351) (351:351:351))
+        (PORT datac (378:378:378) (378:378:378))
+        (PORT datad (1119:1119:1119) (1119:1119:1119))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_4_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2182:2182:2182) (2182:2182:2182))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2068:2068:2068) (2068:2068:2068))
+        (PORT ena (1803:1803:1803) (1803:1803:1803))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_next_1_sqmuxa_2_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (364:364:364))
+        (PORT datab (350:350:350) (350:350:350))
+        (PORT datac (457:457:457) (457:457:457))
+        (PORT datad (363:363:363) (363:363:363))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (363:363:363))
+        (PORT datab (352:352:352) (352:352:352))
+        (PORT datac (460:460:460) (460:460:460))
+        (PORT datad (363:363:363) (363:363:363))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2182:2182:2182) (2182:2182:2182))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2068:2068:2068) (2068:2068:2068))
+        (PORT ena (1803:1803:1803) (1803:1803:1803))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (359:359:359) (359:359:359))
+        (PORT datab (341:341:341) (341:341:341))
+        (PORT datac (1134:1134:1134) (1134:1134:1134))
+        (PORT datad (627:627:627) (627:627:627))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH qfbkin combout (291:291:291) (291:291:291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_3_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1224:1224:1224) (1224:1224:1224))
+        (PORT sclr (1810:1810:1810) (1810:1810:1810))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (PORT ena (1089:1089:1089) (1089:1089:1089))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+        (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_next_1_sqmuxa_1_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1073:1073:1073) (1073:1073:1073))
+        (PORT datab (1044:1044:1044) (1044:1044:1044))
+        (PORT datac (1063:1063:1063) (1063:1063:1063))
+        (PORT datad (676:676:676) (676:676:676))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_3_0_0_0__g0_0_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1084:1084:1084) (1084:1084:1084))
+        (PORT datab (341:341:341) (341:341:341))
+        (PORT datac (371:371:371) (371:371:371))
+        (PORT datad (1029:1029:1029) (1029:1029:1029))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (685:685:685) (685:685:685))
+        (PORT datad (565:565:565) (565:565:565))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_2_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1786:1786:1786) (1786:1786:1786))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (PORT ena (1281:1281:1281) (1281:1281:1281))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (555:555:555) (555:555:555))
+        (PORT datad (434:434:434) (434:434:434))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1786:1786:1786) (1786:1786:1786))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (PORT ena (1281:1281:1281) (1281:1281:1281))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_next_1_sqmuxa_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1393:1393:1393) (1393:1393:1393))
+        (PORT datab (986:986:986) (986:986:986))
+        (PORT datac (4977:4977:4977) (4977:4977:4977))
+        (PORT datad (1255:1255:1255) (1255:1255:1255))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_4.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1218:1218:1218) (1218:1218:1218))
+        (PORT datab (1182:1182:1182) (1182:1182:1182))
+        (PORT datac (1158:1158:1158) (1158:1158:1158))
+        (PORT datad (1459:1459:1459) (1459:1459:1459))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_3.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1223:1223:1223) (1223:1223:1223))
+        (PORT datab (1116:1116:1116) (1116:1116:1116))
+        (PORT datac (1237:1237:1237) (1237:1237:1237))
+        (PORT datad (1195:1195:1195) (1195:1195:1195))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (655:655:655) (655:655:655))
+        (PORT datab (1284:1284:1284) (1284:1284:1284))
+        (PORT datac (1075:1075:1075) (1075:1075:1075))
+        (PORT datad (688:688:688) (688:688:688))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_hsync_state_3_0_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (670:670:670) (670:670:670))
+        (PORT datac (1397:1397:1397) (1397:1397:1397))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|h_sync_1_0_0_0_g1_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (362:362:362))
+        (PORT datab (431:431:431) (431:431:431))
+        (PORT datac (1158:1158:1158) (1158:1158:1158))
+        (PORT datad (430:430:430) (430:430:430))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|h_sync_Z.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1396:1396:1396) (1396:1396:1396))
+        (PORT datab (335:335:335) (335:335:335))
+        (PORT datac (4973:4973:4973) (4973:4973:4973))
+        (PORT datad (994:994:994) (994:994:994))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|h_sync_Z.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1425:1425:1425) (1425:1425:1425))
+        (PORT datab (423:423:423) (423:423:423))
+        (PORT datac (1204:1204:1204) (1204:1204:1204))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1999:1999:1999) (1999:1999:1999))
+        (PORT datac (1294:1294:1294) (1294:1294:1294))
+        (PORT sclr (1848:1848:1848) (1848:1848:1848))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2068:2068:2068) (2068:2068:2068))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (419:419:419) (419:419:419))
+        (PORT datac (1204:1204:1204) (1204:1204:1204))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1999:1999:1999) (1999:1999:1999))
+        (PORT datac (1294:1294:1294) (1294:1294:1294))
+        (PORT sclr (1848:1848:1848) (1848:1848:1848))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2068:2068:2068) (2068:2068:2068))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (444:444:444) (444:444:444))
+        (PORT datac (1203:1203:1203) (1203:1203:1203))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_2_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1999:1999:1999) (1999:1999:1999))
+        (PORT datac (1293:1293:1293) (1293:1293:1293))
+        (PORT sclr (1848:1848:1848) (1848:1848:1848))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2068:2068:2068) (2068:2068:2068))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (437:437:437) (437:437:437))
+        (PORT datac (1202:1202:1202) (1202:1202:1202))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_3_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1999:1999:1999) (1999:1999:1999))
+        (PORT datac (1292:1292:1292) (1292:1292:1292))
+        (PORT sclr (1848:1848:1848) (1848:1848:1848))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2068:2068:2068) (2068:2068:2068))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_6.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1219:1219:1219) (1219:1219:1219))
+        (PORT datab (1422:1422:1422) (1422:1422:1422))
+        (PORT datac (1163:1163:1163) (1163:1163:1163))
+        (PORT datad (1151:1151:1151) (1151:1151:1151))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datac (1202:1202:1202) (1202:1202:1202))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout (551:551:551) (551:551:551))
+        (IOPATH cin0 cout (135:135:135) (135:135:135))
+        (IOPATH cin1 cout (123:123:123) (123:123:123))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_4_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1999:1999:1999) (1999:1999:1999))
+        (PORT datac (1292:1292:1292) (1292:1292:1292))
+        (PORT sclr (1848:1848:1848) (1848:1848:1848))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2068:2068:2068) (2068:2068:2068))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (420:420:420) (420:420:420))
+        (PORT datac (1196:1196:1196) (1196:1196:1196))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_5_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1999:1999:1999) (1999:1999:1999))
+        (PORT datac (1286:1286:1286) (1286:1286:1286))
+        (PORT sclr (1848:1848:1848) (1848:1848:1848))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2068:2068:2068) (2068:2068:2068))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (422:422:422) (422:422:422))
+        (PORT datac (1196:1196:1196) (1196:1196:1196))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_6_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1999:1999:1999) (1999:1999:1999))
+        (PORT datac (1286:1286:1286) (1286:1286:1286))
+        (PORT sclr (1848:1848:1848) (1848:1848:1848))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2068:2068:2068) (2068:2068:2068))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_7_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (436:436:436) (436:436:436))
+        (PORT datac (1195:1195:1195) (1195:1195:1195))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_7_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1999:1999:1999) (1999:1999:1999))
+        (PORT datac (1285:1285:1285) (1285:1285:1285))
+        (PORT sclr (1848:1848:1848) (1848:1848:1848))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2068:2068:2068) (2068:2068:2068))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_8_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datac (1198:1198:1198) (1198:1198:1198))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_8_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1999:1999:1999) (1999:1999:1999))
+        (PORT datac (1288:1288:1288) (1288:1288:1288))
+        (PORT sclr (1848:1848:1848) (1848:1848:1848))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2068:2068:2068) (2068:2068:2068))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_9_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1200:1200:1200) (1200:1200:1200))
+        (PORT datad (432:432:432) (432:432:432))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_9_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1999:1999:1999) (1999:1999:1999))
+        (PORT datac (1290:1290:1290) (1290:1290:1290))
+        (PORT sclr (1848:1848:1848) (1848:1848:1848))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2068:2068:2068) (2068:2068:2068))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_5.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1172:1172:1172) (1172:1172:1172))
+        (PORT datab (1162:1162:1162) (1162:1162:1162))
+        (PORT datac (1162:1162:1162) (1162:1162:1162))
+        (PORT datad (1152:1152:1152) (1152:1152:1152))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (360:360:360))
+        (PORT datab (1125:1125:1125) (1125:1125:1125))
+        (PORT datac (367:367:367) (367:367:367))
+        (PORT datad (1429:1429:1429) (1429:1429:1429))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|G_16.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (706:706:706) (706:706:706))
+        (PORT datab (936:936:936) (936:936:936))
+        (PORT datac (366:366:366) (366:366:366))
+        (PORT datad (450:450:450) (450:450:450))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_7.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1374:1374:1374) (1374:1374:1374))
+        (PORT datab (1146:1146:1146) (1146:1146:1146))
+        (PORT datac (1453:1453:1453) (1453:1453:1453))
+        (PORT datad (1159:1159:1159) (1159:1159:1159))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_6.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1451:1451:1451) (1451:1451:1451))
+        (PORT datab (1349:1349:1349) (1349:1349:1349))
+        (PORT datac (1159:1159:1159) (1159:1159:1159))
+        (PORT datad (1370:1370:1370) (1370:1370:1370))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un14_vsync_counter_8.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (370:370:370))
+        (PORT datad (362:362:362) (362:362:362))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1170:1170:1170) (1170:1170:1170))
+        (PORT datac (1136:1136:1136) (1136:1136:1136))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_5_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2714:2714:2714) (2714:2714:2714))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2058:2058:2058) (2058:2058:2058))
+        (PORT ena (1783:1783:1783) (1783:1783:1783))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_next_1_sqmuxa_1_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1238:1238:1238) (1238:1238:1238))
+        (PORT datab (355:355:355) (355:355:355))
+        (PORT datac (1118:1118:1118) (1118:1118:1118))
+        (PORT datad (1379:1379:1379) (1379:1379:1379))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (443:443:443) (443:443:443))
+        (PORT datab (1291:1291:1291) (1291:1291:1291))
+        (PORT datac (1241:1241:1241) (1241:1241:1241))
+        (PORT datad (1198:1198:1198) (1198:1198:1198))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_4_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2714:2714:2714) (2714:2714:2714))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2058:2058:2058) (2058:2058:2058))
+        (PORT ena (1783:1783:1783) (1783:1783:1783))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_3.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1176:1176:1176) (1176:1176:1176))
+        (PORT datab (1166:1166:1166) (1166:1166:1166))
+        (PORT datac (1161:1161:1161) (1161:1161:1161))
+        (PORT datad (1154:1154:1154) (1154:1154:1154))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_4.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1451:1451:1451) (1451:1451:1451))
+        (PORT datab (827:827:827) (827:827:827))
+        (PORT datac (1230:1230:1230) (1230:1230:1230))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1058:1058:1058) (1058:1058:1058))
+        (PORT datab (441:441:441) (441:441:441))
+        (PORT datac (1088:1088:1088) (1088:1088:1088))
+        (PORT datad (1931:1931:1931) (1931:1931:1931))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2058:2058:2058) (2058:2058:2058))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1239:1239:1239) (1239:1239:1239))
+        (PORT datab (355:355:355) (355:355:355))
+        (PORT datac (1123:1123:1123) (1123:1123:1123))
+        (PORT datad (1380:1380:1380) (1380:1380:1380))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH qfbkin combout (291:291:291) (291:291:291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_3_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1213:1213:1213) (1213:1213:1213))
+        (PORT sclr (1797:1797:1797) (1797:1797:1797))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (PORT ena (1096:1096:1096) (1096:1096:1096))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+        (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_next_1_sqmuxa_2_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1155:1155:1155) (1155:1155:1155))
+        (PORT datac (373:373:373) (373:373:373))
+        (PORT datad (253:253:253) (253:253:253))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_3.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (664:664:664) (664:664:664))
+        (PORT datab (693:693:693) (693:693:693))
+        (PORT datac (686:686:686) (686:686:686))
+        (PORT datad (616:616:616) (616:616:616))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_4.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (339:339:339) (339:339:339))
+        (PORT datac (642:642:642) (642:642:642))
+        (PORT datad (647:647:647) (647:647:647))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_vsync_state_next_1_sqmuxa_0_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (377:377:377) (377:377:377))
+        (PORT datab (350:350:350) (350:350:350))
+        (PORT datac (1177:1177:1177) (1177:1177:1177))
+        (PORT datad (1059:1059:1059) (1059:1059:1059))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_next_2_sqmuxa_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (368:368:368) (368:368:368))
+        (PORT datab (340:340:340) (340:340:340))
+        (PORT datac (571:571:571) (571:571:571))
+        (PORT datad (1022:1022:1022) (1022:1022:1022))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_3_iv_0_0__g0_0_a3_0_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1025:1025:1025) (1025:1025:1025))
+        (PORT datac (1189:1189:1189) (1189:1189:1189))
+        (PORT datad (340:340:340) (340:340:340))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1029:1029:1029) (1029:1029:1029))
+        (PORT datab (419:419:419) (419:419:419))
+        (PORT datac (376:376:376) (376:376:376))
+        (PORT datad (1043:1043:1043) (1043:1043:1043))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|d_set_vsync_counter_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (709:709:709) (709:709:709))
+        (PORT datad (454:454:454) (454:454:454))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_next_1_sqmuxa_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1012:1012:1012) (1012:1012:1012))
+        (PORT datab (356:356:356) (356:356:356))
+        (PORT datac (1189:1189:1189) (1189:1189:1189))
+        (PORT datad (5266:5266:5266) (5266:5266:5266))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1243:1243:1243) (1243:1243:1243))
+        (PORT datab (1127:1127:1127) (1127:1127:1127))
+        (PORT datac (1318:1318:1318) (1318:1318:1318))
+        (PORT datad (1202:1202:1202) (1202:1202:1202))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_2_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2714:2714:2714) (2714:2714:2714))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2058:2058:2058) (2058:2058:2058))
+        (PORT ena (1783:1783:1783) (1783:1783:1783))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_vsync_state_2_0_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1123:1123:1123) (1123:1123:1123))
+        (PORT datac (456:456:456) (456:456:456))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|v_sync_1_0_0_0_g1_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1008:1008:1008) (1008:1008:1008))
+        (PORT datab (435:435:435) (435:435:435))
+        (PORT datac (371:371:371) (371:371:371))
+        (PORT datad (439:439:439) (439:439:439))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|v_sync_Z.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (4836:4836:4836) (4836:4836:4836))
+        (PORT datab (950:950:950) (950:950:950))
+        (PORT datac (365:365:365) (365:365:365))
+        (PORT datad (1457:1457:1457) (1457:1457:1457))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|v_sync_Z.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2058:2058:2058) (2058:2058:2058))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_next_0_sqmuxa_1_1_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1190:1190:1190) (1190:1190:1190))
+        (PORT datab (5263:5263:5263) (5263:5263:5263))
+        (PORT datac (1414:1414:1414) (1414:1414:1414))
+        (PORT datad (466:466:466) (466:466:466))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (415:415:415) (415:415:415))
+        (PORT datad (434:434:434) (434:434:434))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3075:3075:3075) (3075:3075:3075))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1153:1153:1153) (1153:1153:1153))
+        (PORT datab (419:419:419) (419:419:419))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1099:1099:1099) (1099:1099:1099))
+        (PORT datad (349:349:349) (349:349:349))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3098:3098:3098) (3098:3098:3098))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2087:2087:2087) (2087:2087:2087))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1194:1194:1194) (1194:1194:1194))
+        (PORT datab (1151:1151:1151) (1151:1151:1151))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (417:417:417) (417:417:417))
+        (PORT datad (1044:1044:1044) (1044:1044:1044))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_3_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3075:3075:3075) (3075:3075:3075))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (959:959:959) (959:959:959))
+        (PORT datab (1132:1132:1132) (1132:1132:1132))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (706:706:706) (706:706:706))
+        (PORT datab (606:606:606) (606:606:606))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (950:950:950) (950:950:950))
+        (PORT datab (681:681:681) (681:681:681))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (412:412:412) (412:412:412))
+        (PORT datad (538:538:538) (538:538:538))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_4_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3075:3075:3075) (3075:3075:3075))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1172:1172:1172) (1172:1172:1172))
+        (PORT datab (1182:1182:1182) (1182:1182:1182))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (389:389:389) (389:389:389))
+        (PORT datac (1067:1067:1067) (1067:1067:1067))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_5_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3075:3075:3075) (3075:3075:3075))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1365:1365:1365) (1365:1365:1365))
+        (PORT datab (583:583:583) (583:583:583))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (406:406:406) (406:406:406))
+        (PORT datad (554:554:554) (554:554:554))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_6_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3075:3075:3075) (3075:3075:3075))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_7_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1134:1134:1134) (1134:1134:1134))
+        (PORT datab (582:582:582) (582:582:582))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_7_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (359:359:359) (359:359:359))
+        (PORT datac (2328:2328:2328) (2328:2328:2328))
+        (PORT datad (1088:1088:1088) (1088:1088:1088))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_7_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2087:2087:2087) (2087:2087:2087))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_8_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1157:1157:1157) (1157:1157:1157))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_8_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1099:1099:1099) (1099:1099:1099))
+        (PORT datac (2328:2328:2328) (2328:2328:2328))
+        (PORT datad (1064:1064:1064) (1064:1064:1064))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_8_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2087:2087:2087) (2087:2087:2087))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_9_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (438:438:438) (438:438:438))
+        (PORT datad (424:424:424) (424:424:424))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_9_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1101:1101:1101) (1101:1101:1101))
+        (PORT datad (340:340:340) (340:340:340))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_9_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3098:3098:3098) (3098:3098:3098))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2087:2087:2087) (2087:2087:2087))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_2.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (703:703:703) (703:703:703))
+        (PORT datac (688:688:688) (688:688:688))
+        (PORT datad (430:430:430) (430:430:430))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_1.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (425:425:425) (425:425:425))
+        (PORT datad (434:434:434) (434:434:434))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (448:448:448) (448:448:448))
+        (PORT datab (348:348:348) (348:348:348))
+        (PORT datac (367:367:367) (367:367:367))
+        (PORT datad (1144:1144:1144) (1144:1144:1144))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglto9.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1158:1158:1158) (1158:1158:1158))
+        (PORT datab (1113:1113:1113) (1113:1113:1113))
+        (PORT datac (366:366:366) (366:366:366))
+        (PORT datad (1182:1182:1182) (1182:1182:1182))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (417:417:417) (417:417:417))
+        (PORT datad (548:548:548) (548:548:548))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_2_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3075:3075:3075) (3075:3075:3075))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un5_v_enablelto3.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1225:1225:1225) (1225:1225:1225))
+        (PORT datab (1195:1195:1195) (1195:1195:1195))
+        (PORT datac (1386:1386:1386) (1386:1386:1386))
+        (PORT datad (646:646:646) (646:646:646))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un5_v_enablelto5_0.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1182:1182:1182) (1182:1182:1182))
+        (PORT datac (1162:1162:1162) (1162:1162:1162))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un5_v_enablelto7.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (365:365:365) (365:365:365))
+        (PORT datab (928:928:928) (928:928:928))
+        (PORT datac (1380:1380:1380) (1380:1380:1380))
+        (PORT datad (558:558:558) (558:558:558))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datab (2646:2646:2646) (2646:2646:2646))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_next_0_sqmuxa_1_1_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (4838:4838:4838) (4838:4838:4838))
+        (PORT datab (946:946:946) (946:946:946))
+        (PORT datac (454:454:454) (454:454:454))
+        (PORT datad (1460:1460:1460) (1460:1460:1460))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (584:584:584) (584:584:584))
+        (PORT datac (365:365:365) (365:365:365))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3153:3153:3153) (3153:3153:3153))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (635:635:635) (635:635:635))
+        (PORT datab (930:930:930) (930:930:930))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (601:601:601) (601:601:601))
+        (PORT datad (352:352:352) (352:352:352))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_2_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3153:3153:3153) (3153:3153:3153))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_a_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2425:2425:2425) (2425:2425:2425))
+        (PORT datab (667:667:667) (667:667:667))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (670:670:670) (670:670:670))
+        (PORT datab (639:639:639) (639:639:639))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (535:535:535) (535:535:535))
+        (PORT datad (592:592:592) (592:592:592))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3453:3453:3453) (3453:3453:3453))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (654:654:654) (654:654:654))
+        (PORT datab (429:429:429) (429:429:429))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (361:361:361) (361:361:361))
+        (PORT datad (351:351:351) (351:351:351))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_3_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3401:3401:3401) (3401:3401:3401))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (642:642:642) (642:642:642))
+        (PORT datab (608:608:608) (608:608:608))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (587:587:587) (587:587:587))
+        (PORT datac (361:361:361) (361:361:361))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_4_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3153:3153:3153) (3153:3153:3153))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (970:970:970) (970:970:970))
+        (PORT datab (670:670:670) (670:670:670))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (536:536:536) (536:536:536))
+        (PORT datac (542:542:542) (542:542:542))
+        (PORT datad (2675:2675:2675) (2675:2675:2675))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_5_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_8_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (443:443:443) (443:443:443))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_7_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (360:360:360))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_7_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3401:3401:3401) (3401:3401:3401))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_7_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datab (918:918:918) (918:918:918))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_9_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (622:622:622) (622:622:622))
+        (PORT datad (430:430:430) (430:430:430))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_8_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (603:603:603) (603:603:603))
+        (PORT datad (352:352:352) (352:352:352))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_8_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3153:3153:3153) (3153:3153:3153))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglt4_2.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (656:656:656) (656:656:656))
+        (PORT datab (671:671:671) (671:671:671))
+        (PORT datad (434:434:434) (434:434:434))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto5.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (675:675:675) (675:675:675))
+        (PORT datab (647:647:647) (647:647:647))
+        (PORT datac (543:543:543) (543:543:543))
+        (PORT datad (683:683:683) (683:683:683))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto8.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (440:440:440) (440:440:440))
+        (PORT datab (959:959:959) (959:959:959))
+        (PORT datac (1013:1013:1013) (1013:1013:1013))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (602:602:602) (602:602:602))
+        (PORT datad (353:353:353) (353:353:353))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_6_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3153:3153:3153) (3153:3153:3153))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2100:2100:2100) (2100:2100:2100))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un17_v_enablelt2.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (975:975:975) (975:975:975))
+        (PORT datab (963:963:963) (963:963:963))
+        (PORT datad (431:431:431) (431:431:431))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un17_v_enablelto5.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (995:995:995) (995:995:995))
+        (PORT datab (336:336:336) (336:336:336))
+        (PORT datac (611:611:611) (611:611:611))
+        (PORT datad (437:437:437) (437:437:437))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un17_v_enablelto7.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2276:2276:2276) (2276:2276:2276))
+        (PORT datac (2312:2312:2312) (2312:2312:2312))
+        (PORT datad (2449:2449:2449) (2449:2449:2449))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|v_enable_sig_1_0_0_0_g0_i_o4_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (440:440:440) (440:440:440))
+        (PORT datac (1158:1158:1158) (1158:1158:1158))
+        (PORT datad (1008:1008:1008) (1008:1008:1008))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|v_enable_sig_Z.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1133:1133:1133) (1133:1133:1133))
+        (PORT datad (589:589:589) (589:589:589))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|v_enable_sig_Z.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2179:2179:2179) (2179:2179:2179))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2068:2068:2068) (2068:2068:2068))
+        (PORT ena (1783:1783:1783) (1783:1783:1783))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|b_next_0_g0_3_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2480:2480:2480) (2480:2480:2480))
+        (PORT datab (669:669:669) (669:669:669))
+        (PORT datac (2983:2983:2983) (2983:2983:2983))
+        (PORT datad (705:705:705) (705:705:705))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datab (442:442:442) (442:442:442))
+        (PORT datad (1933:1933:1933) (1933:1933:1933))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|h_enable_sig_Z.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3129:3129:3129) (3129:3129:3129))
+        (PORT datad (2427:2427:2427) (2427:2427:2427))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|h_enable_sig_Z.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (4015:4015:4015) (4015:4015:4015))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2087:2087:2087) (2087:2087:2087))
+        (PORT ena (3104:3104:3104) (3104:3104:3104))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un9_v_enablelto6.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1223:1223:1223) (1223:1223:1223))
+        (PORT datab (1285:1285:1285) (1285:1285:1285))
+        (PORT datac (1208:1208:1208) (1208:1208:1208))
+        (PORT datad (1448:1448:1448) (1448:1448:1448))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un9_v_enablelto9.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (718:718:718) (718:718:718))
+        (PORT datab (928:928:928) (928:928:928))
+        (PORT datac (687:687:687) (687:687:687))
+        (PORT datad (347:347:347) (347:347:347))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (425:425:425) (425:425:425))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1160:1160:1160) (1160:1160:1160))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (941:941:941) (941:941:941))
+        (PORT datab (419:419:419) (419:419:419))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1347:1347:1347) (1347:1347:1347))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|un2_toggle_counter_next_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (605:605:605) (605:605:605))
+        (PORT datab (930:930:930) (930:930:930))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (688:688:688) (688:688:688))
+        (PORT datab (419:419:419) (419:419:419))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_2_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1648:1648:1648) (1648:1648:1648))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (681:681:681) (681:681:681))
+        (PORT datab (419:419:419) (419:419:419))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_3_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1347:1347:1347) (1347:1347:1347))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (444:444:444) (444:444:444))
+        (PORT datab (624:624:624) (624:624:624))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_4_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1648:1648:1648) (1648:1648:1648))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (438:438:438) (438:438:438))
+        (PORT datab (609:609:609) (609:609:609))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_5_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1347:1347:1347) (1347:1347:1347))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_7_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (698:698:698) (698:698:698))
+        (PORT datab (903:903:903) (903:903:903))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_7_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1347:1347:1347) (1347:1347:1347))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (437:437:437) (437:437:437))
+        (PORT datab (601:601:601) (601:601:601))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_6_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1648:1648:1648) (1648:1648:1648))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_9_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (626:626:626) (626:626:626))
+        (PORT datab (940:940:940) (940:940:940))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout (551:551:551) (551:551:551))
+        (IOPATH datab cout (460:460:460) (460:460:460))
+        (IOPATH cin0 cout (135:135:135) (135:135:135))
+        (IOPATH cin1 cout (123:123:123) (123:123:123))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_9_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1347:1347:1347) (1347:1347:1347))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_8_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datab (586:586:586) (586:586:586))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout (551:551:551) (551:551:551))
+        (IOPATH datab cout (460:460:460) (460:460:460))
+        (IOPATH cin0 cout (135:135:135) (135:135:135))
+        (IOPATH cin1 cout (123:123:123) (123:123:123))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_8_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1648:1648:1648) (1648:1648:1648))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto7_4.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (918:918:918) (918:918:918))
+        (PORT datab (601:601:601) (601:601:601))
+        (PORT datac (623:623:623) (623:623:623))
+        (PORT datad (986:986:986) (986:986:986))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto7.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (612:612:612) (612:612:612))
+        (PORT datab (909:909:909) (909:909:909))
+        (PORT datac (372:372:372) (372:372:372))
+        (PORT datad (982:982:982) (982:982:982))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_11_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (616:616:616) (616:616:616))
+        (PORT datab (420:420:420) (420:420:420))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_11_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1347:1347:1347) (1347:1347:1347))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_10_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (622:622:622) (622:622:622))
+        (PORT datab (420:420:420) (420:420:420))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_10_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1648:1648:1648) (1648:1648:1648))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto10.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (971:971:971) (971:971:971))
+        (PORT datab (339:339:339) (339:339:339))
+        (PORT datac (631:631:631) (631:631:631))
+        (PORT datad (971:971:971) (971:971:971))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_12_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (963:963:963) (963:963:963))
+        (PORT datab (416:416:416) (416:416:416))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_12_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1648:1648:1648) (1648:1648:1648))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_13_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (649:649:649) (649:649:649))
+        (PORT datab (679:679:679) (679:679:679))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_13_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1347:1347:1347) (1347:1347:1347))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_15_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (670:670:670) (670:670:670))
+        (PORT datab (603:603:603) (603:603:603))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_15_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1347:1347:1347) (1347:1347:1347))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_14_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (436:436:436) (436:436:436))
+        (PORT datab (943:943:943) (943:943:943))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_14_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1648:1648:1648) (1648:1648:1648))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_17_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (439:439:439) (439:439:439))
+        (PORT datab (628:628:628) (628:628:628))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_17_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1347:1347:1347) (1347:1347:1347))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_16_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datab (585:585:585) (585:585:585))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_16_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1648:1648:1648) (1648:1648:1648))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_18_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (426:426:426) (426:426:426))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_18_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1648:1648:1648) (1648:1648:1648))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_19_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (419:419:419) (419:419:419))
+        (PORT datad (660:660:660) (660:660:660))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_19_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1347:1347:1347) (1347:1347:1347))
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto19_4.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (952:952:952) (952:952:952))
+        (PORT datab (600:600:600) (600:600:600))
+        (PORT datac (630:630:630) (630:630:630))
+        (PORT datad (988:988:988) (988:988:988))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto19_5.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (944:944:944) (944:944:944))
+        (PORT datab (343:343:343) (343:343:343))
+        (PORT datac (586:586:586) (586:586:586))
+        (PORT datad (952:952:952) (952:952:952))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto19.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (370:370:370))
+        (PORT datab (935:935:935) (935:935:935))
+        (PORT datac (361:361:361) (361:361:361))
+        (PORT datad (993:993:993) (993:993:993))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_sig_0_0_0_g1_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_sig_Z.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (447:447:447) (447:447:447))
+        (PORT datad (359:359:359) (359:359:359))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_sig_Z.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (5625:5625:5625) (5625:5625:5625))
+        (PORT clk (2107:2107:2107) (2107:2107:2107))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|b_next_0_g0_5_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (364:364:364))
+        (PORT datab (421:421:421) (421:421:421))
+        (PORT datac (367:367:367) (367:367:367))
+        (PORT datad (2041:2041:2041) (2041:2041:2041))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un13_v_enablelto8_a.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (996:996:996) (996:996:996))
+        (PORT datab (963:963:963) (963:963:963))
+        (PORT datac (609:609:609) (609:609:609))
+        (PORT datad (438:438:438) (438:438:438))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un13_v_enablelto8.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2988:2988:2988) (2988:2988:2988))
+        (PORT datab (2095:2095:2095) (2095:2095:2095))
+        (PORT datac (2317:2317:2317) (2317:2317:2317))
+        (PORT datad (2279:2279:2279) (2279:2279:2279))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|b_Z.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (368:368:368) (368:368:368))
+        (PORT datab (338:338:338) (338:338:338))
+        (PORT datac (365:365:365) (365:365:365))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|b_Z.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (5508:5508:5508) (5508:5508:5508))
+        (PORT clk (2087:2087:2087) (2087:2087:2087))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2835:2835:2835) (2835:2835:2835))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2467:2467:2467) (2467:2467:2467))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_set_column_counter_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (4462:4462:4462) (4462:4462:4462))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_set_line_counter_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2677:2677:2677) (2677:2677:2677))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_set_hsync_counter_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3353:3353:3353) (3353:3353:3353))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_set_vsync_counter_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2678:2678:2678) (2678:2678:2678))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_r_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3050:3050:3050) (3050:3050:3050))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_g_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3087:3087:3087) (3087:3087:3087))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_b_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2395:2395:2395) (2395:2395:2395))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_h_enable_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2375:2375:2375) (2375:2375:2375))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_v_enable_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2344:2344:2344) (2344:2344:2344))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_state_clk_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2239:2239:2239) (2239:2239:2239))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2657:2657:2657) (2657:2657:2657))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|r0_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2648:2648:2648) (2648:2648:2648))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|r1_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3318:3318:3318) (3318:3318:3318))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|r2_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3333:3333:3333) (3333:3333:3333))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|g0_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2616:2616:2616) (2616:2616:2616))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|g1_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3318:3318:3318) (3318:3318:3318))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|g2_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3645:3645:3645) (3645:3645:3645))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|b0_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3422:3422:3422) (3422:3422:3422))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|b1_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3154:3154:3154) (3154:3154:3154))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|hsync_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2326:2326:2326) (2326:2326:2326))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|vsync_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2317:2317:2317) (2317:2317:2317))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_9_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2572:2572:2572) (2572:2572:2572))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_8_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1976:1976:1976) (1976:1976:1976))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_7_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2835:2835:2835) (2835:2835:2835))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2551:2551:2551) (2551:2551:2551))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3073:3073:3073) (3073:3073:3073))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2381:2381:2381) (2381:2381:2381))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2126:2126:2126) (2126:2126:2126))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2189:2189:2189) (2189:2189:2189))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2364:2364:2364) (2364:2364:2364))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2598:2598:2598) (2598:2598:2598))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_9_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2678:2678:2678) (2678:2678:2678))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_8_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2607:2607:2607) (2607:2607:2607))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_7_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3076:3076:3076) (3076:3076:3076))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1386:1386:1386) (1386:1386:1386))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1827:1827:1827) (1827:1827:1827))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1860:1860:1860) (1860:1860:1860))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1381:1381:1381) (1381:1381:1381))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1810:1810:1810) (1810:1810:1810))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2662:2662:2662) (2662:2662:2662))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1864:1864:1864) (1864:1864:1864))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_state_out_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3694:3694:3694) (3694:3694:3694))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_state_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3419:3419:3419) (3419:3419:3419))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_state_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2788:2788:2788) (2788:2788:2788))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_state_out_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3562:3562:3562) (3562:3562:3562))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_state_out_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1438:1438:1438) (1438:1438:1438))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_state_out_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1639:1639:1639) (1639:1639:1639))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_state_out_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2473:2473:2473) (2473:2473:2473))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_8_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (4304:4304:4304) (4304:4304:4304))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_7_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2862:2862:2862) (2862:2862:2862))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1400:1400:1400) (1400:1400:1400))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
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+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1626:1626:1626) (1626:1626:1626))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1391:1391:1391) (1391:1391:1391))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1595:1595:1595) (1595:1595:1595))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3803:3803:3803) (3803:3803:3803))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1623:1623:1623) (1623:1623:1623))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1574:1574:1574) (1574:1574:1574))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_24_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3665:3665:3665) (3665:3665:3665))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_23_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2613:2613:2613) (2613:2613:2613))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_22_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2613:2613:2613) (2613:2613:2613))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_21_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3252:3252:3252) (3252:3252:3252))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_20_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3252:3252:3252) (3252:3252:3252))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_19_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2635:2635:2635) (2635:2635:2635))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_18_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1917:1917:1917) (1917:1917:1917))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_17_\~I.inst1)
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+      (ABSOLUTE
+        (PORT datain (2371:2371:2371) (2371:2371:2371))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_16_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2392:2392:2392) (2392:2392:2392))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_15_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2144:2144:2144) (2144:2144:2144))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_14_\~I.inst1)
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+      (ABSOLUTE
+        (PORT datain (1938:1938:1938) (1938:1938:1938))
+        (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_13_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1612:1612:1612) (1612:1612:1612))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_12_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2195:2195:2195) (2195:2195:2195))
+        (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_11_\~I.inst1)
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+      (ABSOLUTE
+        (PORT datain (2135:2135:2135) (2135:2135:2135))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_10_\~I.inst1)
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+      (ABSOLUTE
+        (PORT datain (2011:2011:2011) (2011:2011:2011))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_9_\~I.inst1)
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+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
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+  (CELL
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+    (INSTANCE inst\|d_toggle_counter_out_8_\~I.inst1)
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+      (ABSOLUTE
+        (PORT datain (1587:1587:1587) (1587:1587:1587))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_7_\~I.inst1)
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+      (ABSOLUTE
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+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_6_\~I.inst1)
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+      (ABSOLUTE
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+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
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+  (CELL
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+    (INSTANCE inst\|d_toggle_counter_out_5_\~I.inst1)
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+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
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+    (INSTANCE inst\|d_toggle_counter_out_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3292:3292:3292) (3292:3292:3292))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2140:2140:2140) (2140:2140:2140))
+        (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1348:1348:1348) (1348:1348:1348))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1884:1884:1884) (1884:1884:1884))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2306:2306:2306) (2306:2306:2306))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_9_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1904:1904:1904) (1904:1904:1904))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_8_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1632:1632:1632) (1632:1632:1632))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_7_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2569:2569:2569) (2569:2569:2569))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1678:1678:1678) (1678:1678:1678))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1353:1353:1353) (1353:1353:1353))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2323:2323:2323) (2323:2323:2323))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1691:1691:1691) (1691:1691:1691))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1362:1362:1362) (1362:1362:1362))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1707:1707:1707) (1707:1707:1707))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1707:1707:1707) (1707:1707:1707))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_state_out_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2026:2026:2026) (2026:2026:2026))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_state_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2390:2390:2390) (2390:2390:2390))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_state_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2411:2411:2411) (2411:2411:2411))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_state_out_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3831:3831:3831) (3831:3831:3831))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_state_out_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3341:3341:3341) (3341:3341:3341))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_state_out_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2625:2625:2625) (2625:2625:2625))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_state_out_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3295:3295:3295) (3295:3295:3295))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_tri_13_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3346:3346:3346) (3346:3346:3346))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_12_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (5257:5257:5257) (5257:5257:5257))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_11_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3140:3140:3140) (3140:3140:3140))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_10_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3134:3134:3134) (3134:3134:3134))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_9_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2980:2980:2980) (2980:2980:2980))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_8_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2960:2960:2960) (2960:2960:2960))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_7_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (5262:5262:5262) (5262:5262:5262))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_tri_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3618:3618:3618) (3618:3618:3618))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_tri_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3618:3618:3618) (3618:3618:3618))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_tri_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3378:3378:3378) (3378:3378:3378))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_tri_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3378:3378:3378) (3378:3378:3378))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3946:3946:3946) (3946:3946:3946))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3140:3140:3140) (3140:3140:3140))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_tri_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3291:3291:3291) (3291:3291:3291))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+)