--- /dev/null
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions
+// and other software and tools, and its AMPP partner logic
+// functions, and any output files from any of the foregoing
+// (including device programming or simulation files), and any
+// associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License
+// Subscription Agreement, Altera MegaCore Function License
+// Agreement, or other applicable license agreement, including,
+// without limitation, that your use is for the sole purpose of
+// programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II"
+// VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version"
+
+// DATE "11/03/2009 17:37:43"
+
+//
+// Device: Altera EP1S25F672C6 Package FBGA672
+//
+
+//
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+//
+
+`timescale 1 ps/ 1 ps
+
+module vga_pll (
+ d_hsync,
+ board_clk,
+ reset,
+ d_vsync,
+ d_set_column_counter,
+ d_set_line_counter,
+ d_set_hsync_counter,
+ d_set_vsync_counter,
+ d_r,
+ d_g,
+ d_b,
+ d_h_enable,
+ d_v_enable,
+ d_state_clk,
+ d_toggle,
+ r0_pin,
+ r1_pin,
+ r2_pin,
+ g0_pin,
+ g1_pin,
+ g2_pin,
+ b0_pin,
+ b1_pin,
+ hsync_pin,
+ vsync_pin,
+ d_column_counter,
+ d_hsync_counter,
+ d_hsync_state,
+ d_line_counter,
+ d_toggle_counter,
+ d_vsync_counter,
+ d_vsync_state,
+ seven_seg_pin);
+output d_hsync;
+input board_clk;
+input reset;
+output d_vsync;
+output d_set_column_counter;
+output d_set_line_counter;
+output d_set_hsync_counter;
+output d_set_vsync_counter;
+output d_r;
+output d_g;
+output d_b;
+output d_h_enable;
+output d_v_enable;
+output d_state_clk;
+output d_toggle;
+output r0_pin;
+output r1_pin;
+output r2_pin;
+output g0_pin;
+output g1_pin;
+output g2_pin;
+output b0_pin;
+output b1_pin;
+output hsync_pin;
+output vsync_pin;
+output [9:0] d_column_counter;
+output [9:0] d_hsync_counter;
+output [0:6] d_hsync_state;
+output [8:0] d_line_counter;
+output [24:0] d_toggle_counter;
+output [9:0] d_vsync_counter;
+output [0:6] d_vsync_state;
+output [13:0] seven_seg_pin;
+
+wire gnd = 1'b0;
+wire vcc = 1'b1;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+// synopsys translate_off
+initial $sdf_annotate("vga_pll_v.sdo");
+// synopsys translate_on
+
+wire \inst1|altpll_component|pll~CLK1 ;
+wire \inst1|altpll_component|pll~CLK2 ;
+wire \inst1|altpll_component|pll~CLK3 ;
+wire \inst1|altpll_component|pll~CLK4 ;
+wire \inst1|altpll_component|pll~CLK5 ;
+wire \inst|vga_control_unit|un2_toggle_counter_next_0_~COMBOUT ;
+wire \inst|vga_driver_unit|un2_column_counter_next_0_~COMBOUT ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT ;
+wire \board_clk~combout ;
+wire \inst1|altpll_component|_clk0 ;
+wire \reset~combout ;
+wire \inst|vga_driver_unit|un6_dly_counter_0_x ;
+wire \inst|vga_driver_unit|hsync_state_6 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 ;
+wire \inst|vga_driver_unit|hsync_counter_1 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 ;
+wire \inst|vga_driver_unit|hsync_counter_2 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 ;
+wire \inst|vga_driver_unit|hsync_counter_3 ;
+wire \inst|vga_driver_unit|un13_hsync_counter_7 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 ;
+wire \inst|vga_driver_unit|hsync_counter_4 ;
+wire \inst|vga_driver_unit|hsync_counter_5 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ;
+wire \inst|vga_driver_unit|hsync_counter_6 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 ;
+wire \inst|vga_driver_unit|hsync_counter_8 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 ;
+wire \inst|vga_driver_unit|hsync_counter_9 ;
+wire \inst|vga_driver_unit|un9_hsync_counterlt9_3 ;
+wire \inst|vga_driver_unit|un9_hsync_counterlt9 ;
+wire \inst|vga_driver_unit|G_2_i ;
+wire \inst|vga_driver_unit|hsync_counter_7 ;
+wire \inst|vga_driver_unit|un13_hsync_counter_2 ;
+wire \inst|vga_driver_unit|un13_hsync_counter ;
+wire \inst|vga_driver_unit|un11_hsync_counter_3 ;
+wire \inst|vga_driver_unit|un11_hsync_counter_2 ;
+wire \inst|vga_driver_unit|un10_hsync_counter_1 ;
+wire \inst|vga_driver_unit|un10_hsync_counter_4 ;
+wire \inst|vga_driver_unit|un10_hsync_counter_3 ;
+wire \inst|vga_driver_unit|hsync_state_5 ;
+wire \inst|vga_driver_unit|hsync_state_4 ;
+wire \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 ;
+wire \inst|vga_driver_unit|hsync_state_1 ;
+wire \inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 ;
+wire \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 ;
+wire \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ;
+wire \inst|vga_driver_unit|hsync_state_2 ;
+wire \inst|vga_driver_unit|hsync_state_0 ;
+wire \inst|vga_driver_unit|d_set_hsync_counter ;
+wire \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ;
+wire \inst|vga_driver_unit|hsync_counter_0 ;
+wire \inst|vga_driver_unit|un12_hsync_counter_4 ;
+wire \inst|vga_driver_unit|un12_hsync_counter_3 ;
+wire \inst|vga_driver_unit|un12_hsync_counter ;
+wire \inst|vga_driver_unit|hsync_state_3 ;
+wire \inst|vga_driver_unit|un1_hsync_state_3_0 ;
+wire \inst|vga_driver_unit|h_sync_1_0_0_0_g1 ;
+wire \inst|vga_driver_unit|h_sync ;
+wire \inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 ;
+wire \inst|vga_driver_unit|vsync_counter_1 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 ;
+wire \inst|vga_driver_unit|vsync_counter_2 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 ;
+wire \inst|vga_driver_unit|vsync_counter_3 ;
+wire \inst|vga_driver_unit|un9_vsync_counterlt9_6 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 ;
+wire \inst|vga_driver_unit|vsync_counter_5 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ;
+wire \inst|vga_driver_unit|vsync_counter_6 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 ;
+wire \inst|vga_driver_unit|vsync_counter_7 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 ;
+wire \inst|vga_driver_unit|vsync_counter_8 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 ;
+wire \inst|vga_driver_unit|vsync_counter_9 ;
+wire \inst|vga_driver_unit|un9_vsync_counterlt9_5 ;
+wire \inst|vga_driver_unit|un9_vsync_counterlt9 ;
+wire \inst|vga_driver_unit|vsync_state_6 ;
+wire \inst|vga_driver_unit|G_16_i ;
+wire \inst|vga_driver_unit|vsync_counter_4 ;
+wire \inst|vga_driver_unit|un12_vsync_counter_7 ;
+wire \inst|vga_driver_unit|un12_vsync_counter_6 ;
+wire \inst|vga_driver_unit|un14_vsync_counter_8 ;
+wire \inst|vga_driver_unit|vsync_state_5 ;
+wire \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 ;
+wire \inst|vga_driver_unit|vsync_state_4 ;
+wire \inst|vga_driver_unit|un13_vsync_counter_3 ;
+wire \inst|vga_driver_unit|un13_vsync_counter_4 ;
+wire \inst|vga_driver_unit|vsync_state_1 ;
+wire \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 ;
+wire \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 ;
+wire \inst|vga_driver_unit|un15_vsync_counter_3 ;
+wire \inst|vga_driver_unit|un15_vsync_counter_4 ;
+wire \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 ;
+wire \inst|vga_driver_unit|vsync_state_next_2_sqmuxa ;
+wire \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 ;
+wire \inst|vga_driver_unit|vsync_state_0 ;
+wire \inst|vga_driver_unit|d_set_vsync_counter ;
+wire \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ;
+wire \inst|vga_driver_unit|vsync_counter_0 ;
+wire \inst|vga_driver_unit|vsync_state_3 ;
+wire \inst|vga_driver_unit|vsync_state_2 ;
+wire \inst|vga_driver_unit|un1_vsync_state_2_0 ;
+wire \inst|vga_driver_unit|v_sync_1_0_0_0_g1 ;
+wire \inst|vga_driver_unit|v_sync ;
+wire \~STRATIX_FITTER_CREATED_GND~I_combout ;
+wire \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ;
+wire \inst|vga_driver_unit|column_counter_sig_0 ;
+wire \inst|vga_driver_unit|column_counter_sig_1 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 ;
+wire \inst|vga_driver_unit|column_counter_sig_3 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 ;
+wire \inst|vga_driver_unit|column_counter_sig_4 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 ;
+wire \inst|vga_driver_unit|column_counter_sig_5 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 ;
+wire \inst|vga_driver_unit|column_counter_sig_6 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 ;
+wire \inst|vga_driver_unit|column_counter_sig_7 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 ;
+wire \inst|vga_driver_unit|column_counter_sig_8 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 ;
+wire \inst|vga_driver_unit|column_counter_sig_9 ;
+wire \inst|vga_driver_unit|un10_column_counter_siglt6_2 ;
+wire \inst|vga_driver_unit|un10_column_counter_siglt6_1 ;
+wire \inst|vga_driver_unit|un10_column_counter_siglt6 ;
+wire \inst|vga_driver_unit|un10_column_counter_siglto9 ;
+wire \inst|vga_driver_unit|column_counter_sig_2 ;
+wire \inst|vga_control_unit|un5_v_enablelto3 ;
+wire \inst|vga_control_unit|un5_v_enablelto5_0 ;
+wire \inst|vga_control_unit|un5_v_enablelto7 ;
+wire \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ;
+wire \inst|vga_driver_unit|line_counter_sig_0 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 ;
+wire \inst|vga_driver_unit|line_counter_sig_2 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 ;
+wire \inst|vga_driver_unit|line_counter_sig_1 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 ;
+wire \inst|vga_driver_unit|line_counter_sig_3 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 ;
+wire \inst|vga_driver_unit|line_counter_sig_4 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 ;
+wire \inst|vga_driver_unit|line_counter_sig_5 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 ;
+wire \inst|vga_driver_unit|line_counter_sig_7 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 ;
+wire \inst|vga_driver_unit|line_counter_sig_8 ;
+wire \inst|vga_driver_unit|un10_line_counter_siglt4_2 ;
+wire \inst|vga_driver_unit|un10_line_counter_siglto5 ;
+wire \inst|vga_driver_unit|un10_line_counter_siglto8 ;
+wire \inst|vga_driver_unit|line_counter_sig_6 ;
+wire \inst|vga_control_unit|un17_v_enablelt2 ;
+wire \inst|vga_control_unit|un17_v_enablelto5 ;
+wire \inst|vga_control_unit|un17_v_enablelto7 ;
+wire \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ;
+wire \inst|vga_driver_unit|v_enable_sig ;
+wire \inst|vga_control_unit|b_next_0_g0_3 ;
+wire \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ;
+wire \inst|vga_driver_unit|h_enable_sig ;
+wire \inst|vga_control_unit|un9_v_enablelto6 ;
+wire \inst|vga_control_unit|un9_v_enablelto9 ;
+wire \inst|vga_control_unit|toggle_counter_sig_0 ;
+wire \inst|vga_control_unit|toggle_counter_sig_1 ;
+wire \inst|vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3 ;
+wire \inst|vga_control_unit|toggle_counter_sig_2 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17 ;
+wire \inst|vga_control_unit|toggle_counter_sig_3 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33 ;
+wire \inst|vga_control_unit|toggle_counter_sig_4 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19 ;
+wire \inst|vga_control_unit|toggle_counter_sig_5 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21 ;
+wire \inst|vga_control_unit|toggle_counter_sig_7 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35 ;
+wire \inst|vga_control_unit|toggle_counter_sig_6 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23 ;
+wire \inst|vga_control_unit|toggle_counter_sig_9 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37 ;
+wire \inst|vga_control_unit|toggle_counter_sig_8 ;
+wire \inst|vga_control_unit|un1_toggle_counter_siglto7_4 ;
+wire \inst|vga_control_unit|un1_toggle_counter_siglto7 ;
+wire \inst|vga_control_unit|toggle_counter_sig_11 ;
+wire \inst|vga_control_unit|toggle_counter_sig_10 ;
+wire \inst|vga_control_unit|un1_toggle_counter_siglto10 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39 ;
+wire \inst|vga_control_unit|toggle_counter_sig_12 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25 ;
+wire \inst|vga_control_unit|toggle_counter_sig_13 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27 ;
+wire \inst|vga_control_unit|toggle_counter_sig_15 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41 ;
+wire \inst|vga_control_unit|toggle_counter_sig_14 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29 ;
+wire \inst|vga_control_unit|toggle_counter_sig_17 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43 ;
+wire \inst|vga_control_unit|toggle_counter_sig_16 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45 ;
+wire \inst|vga_control_unit|toggle_counter_sig_18 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31 ;
+wire \inst|vga_control_unit|toggle_counter_sig_19 ;
+wire \inst|vga_control_unit|un1_toggle_counter_siglto19_4 ;
+wire \inst|vga_control_unit|un1_toggle_counter_siglto19_5 ;
+wire \inst|vga_control_unit|un1_toggle_counter_siglto19 ;
+wire \inst|vga_control_unit|toggle_sig_0_0_0_g1 ;
+wire \inst|vga_control_unit|toggle_sig ;
+wire \inst|vga_control_unit|b_next_0_g0_5 ;
+wire \inst|vga_control_unit|un13_v_enablelto8_a ;
+wire \inst|vga_control_unit|un13_v_enablelto8 ;
+wire \inst|vga_control_unit|b ;
+wire [17:1] \inst|vga_control_unit|toggle_counter_sig_cout ;
+wire [0:0] \inst|vga_control_unit|un2_toggle_counter_next_cout ;
+wire [8:0] \inst|vga_driver_unit|hsync_counter_cout ;
+wire [1:1] \inst|vga_driver_unit|un1_line_counter_sig_a_cout ;
+wire [9:1] \inst|vga_driver_unit|un1_line_counter_sig_combout ;
+wire [7:1] \inst|vga_driver_unit|un1_line_counter_sig_cout ;
+wire [9:1] \inst|vga_driver_unit|un2_column_counter_next_combout ;
+wire [7:0] \inst|vga_driver_unit|un2_column_counter_next_cout ;
+wire [8:0] \inst|vga_driver_unit|vsync_counter_cout ;
+wire [1:0] \inst|dly_counter ;
+
+wire [5:0] \inst1|altpll_component|pll_CLK_bus ;
+
+assign \inst1|altpll_component|_clk0 = \inst1|altpll_component|pll_CLK_bus [0];
+assign \inst1|altpll_component|pll~CLK1 = \inst1|altpll_component|pll_CLK_bus [1];
+assign \inst1|altpll_component|pll~CLK2 = \inst1|altpll_component|pll_CLK_bus [2];
+assign \inst1|altpll_component|pll~CLK3 = \inst1|altpll_component|pll_CLK_bus [3];
+assign \inst1|altpll_component|pll~CLK4 = \inst1|altpll_component|pll_CLK_bus [4];
+assign \inst1|altpll_component|pll~CLK5 = \inst1|altpll_component|pll_CLK_bus [5];
+
+// atom is at PIN_N3
+stratix_io \board_clk~I (
+ .datain(gnd),
+ .ddiodatain(gnd),
+ .oe(gnd),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(\board_clk~combout ),
+ .regout(),
+ .ddioregout(),
+ .padio(board_clk),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \board_clk~I .ddio_mode = "none";
+defparam \board_clk~I .input_async_reset = "none";
+defparam \board_clk~I .input_power_up = "low";
+defparam \board_clk~I .input_register_mode = "none";
+defparam \board_clk~I .input_sync_reset = "none";
+defparam \board_clk~I .oe_async_reset = "none";
+defparam \board_clk~I .oe_power_up = "low";
+defparam \board_clk~I .oe_register_mode = "none";
+defparam \board_clk~I .oe_sync_reset = "none";
+defparam \board_clk~I .operation_mode = "input";
+defparam \board_clk~I .output_async_reset = "none";
+defparam \board_clk~I .output_power_up = "low";
+defparam \board_clk~I .output_register_mode = "none";
+defparam \board_clk~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PLL_1
+stratix_pll \inst1|altpll_component|pll (
+ .fbin(vcc),
+ .ena(vcc),
+ .clkswitch(gnd),
+ .areset(gnd),
+ .pfdena(vcc),
+ .scanclk(gnd),
+ .scanaclr(gnd),
+ .scandata(gnd),
+ .comparator(gnd),
+ .inclk({gnd,\board_clk~combout }),
+ .clkena(6'b111111),
+ .extclkena(4'b1111),
+ .activeclock(),
+ .clkloss(),
+ .locked(),
+ .scandataout(),
+ .enable0(),
+ .enable1(),
+ .clk(\inst1|altpll_component|pll_CLK_bus ),
+ .extclk(),
+ .clkbad());
+// synopsys translate_off
+defparam \inst1|altpll_component|pll .clk0_counter = "g0";
+defparam \inst1|altpll_component|pll .clk0_divide_by = 38;
+defparam \inst1|altpll_component|pll .clk0_duty_cycle = 50;
+defparam \inst1|altpll_component|pll .clk0_multiply_by = 31;
+defparam \inst1|altpll_component|pll .clk0_phase_shift = "-725";
+defparam \inst1|altpll_component|pll .clk1_divide_by = 1;
+defparam \inst1|altpll_component|pll .clk1_duty_cycle = 50;
+defparam \inst1|altpll_component|pll .clk1_multiply_by = 1;
+defparam \inst1|altpll_component|pll .clk1_phase_shift = "0";
+defparam \inst1|altpll_component|pll .clk2_divide_by = 1;
+defparam \inst1|altpll_component|pll .clk2_duty_cycle = 50;
+defparam \inst1|altpll_component|pll .clk2_multiply_by = 1;
+defparam \inst1|altpll_component|pll .clk2_phase_shift = "0";
+defparam \inst1|altpll_component|pll .compensate_clock = "clk0";
+defparam \inst1|altpll_component|pll .enable_switch_over_counter = "off";
+defparam \inst1|altpll_component|pll .g0_high = 10;
+defparam \inst1|altpll_component|pll .g0_initial = 1;
+defparam \inst1|altpll_component|pll .g0_low = 9;
+defparam \inst1|altpll_component|pll .g0_mode = "odd";
+defparam \inst1|altpll_component|pll .g0_ph = 0;
+defparam \inst1|altpll_component|pll .gate_lock_counter = 0;
+defparam \inst1|altpll_component|pll .gate_lock_signal = "no";
+defparam \inst1|altpll_component|pll .inclk0_input_frequency = 30003;
+defparam \inst1|altpll_component|pll .inclk1_input_frequency = 30003;
+defparam \inst1|altpll_component|pll .invalid_lock_multiplier = 5;
+defparam \inst1|altpll_component|pll .l0_high = 13;
+defparam \inst1|altpll_component|pll .l0_initial = 1;
+defparam \inst1|altpll_component|pll .l0_low = 13;
+defparam \inst1|altpll_component|pll .l0_mode = "even";
+defparam \inst1|altpll_component|pll .l0_ph = 0;
+defparam \inst1|altpll_component|pll .l1_mode = "bypass";
+defparam \inst1|altpll_component|pll .l1_ph = 0;
+defparam \inst1|altpll_component|pll .m = 31;
+defparam \inst1|altpll_component|pll .m_initial = 1;
+defparam \inst1|altpll_component|pll .m_ph = 3;
+defparam \inst1|altpll_component|pll .n = 2;
+defparam \inst1|altpll_component|pll .operation_mode = "normal";
+defparam \inst1|altpll_component|pll .pfd_max = 100000;
+defparam \inst1|altpll_component|pll .pfd_min = 2000;
+defparam \inst1|altpll_component|pll .pll_compensation_delay = 1713;
+defparam \inst1|altpll_component|pll .pll_type = "fast";
+defparam \inst1|altpll_component|pll .primary_clock = "inclk0";
+defparam \inst1|altpll_component|pll .qualify_conf_done = "off";
+defparam \inst1|altpll_component|pll .simulation_type = "timing";
+defparam \inst1|altpll_component|pll .skip_vco = "off";
+defparam \inst1|altpll_component|pll .switch_over_counter = 1;
+defparam \inst1|altpll_component|pll .switch_over_on_gated_lock = "off";
+defparam \inst1|altpll_component|pll .switch_over_on_lossclk = "off";
+defparam \inst1|altpll_component|pll .valid_lock_multiplier = 1;
+defparam \inst1|altpll_component|pll .vco_center = 1250;
+defparam \inst1|altpll_component|pll .vco_max = 3334;
+defparam \inst1|altpll_component|pll .vco_min = 1000;
+// synopsys translate_on
+
+// atom is at PIN_A5
+stratix_io \inst|reset_pin_in~I (
+ .datain(gnd),
+ .ddiodatain(gnd),
+ .oe(gnd),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(\reset~combout ),
+ .regout(),
+ .ddioregout(),
+ .padio(reset),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|reset_pin_in~I .ddio_mode = "none";
+defparam \inst|reset_pin_in~I .input_async_reset = "none";
+defparam \inst|reset_pin_in~I .input_power_up = "low";
+defparam \inst|reset_pin_in~I .input_register_mode = "none";
+defparam \inst|reset_pin_in~I .input_sync_reset = "none";
+defparam \inst|reset_pin_in~I .oe_async_reset = "none";
+defparam \inst|reset_pin_in~I .oe_power_up = "low";
+defparam \inst|reset_pin_in~I .oe_register_mode = "none";
+defparam \inst|reset_pin_in~I .oe_sync_reset = "none";
+defparam \inst|reset_pin_in~I .operation_mode = "input";
+defparam \inst|reset_pin_in~I .output_async_reset = "none";
+defparam \inst|reset_pin_in~I .output_power_up = "low";
+defparam \inst|reset_pin_in~I .output_register_mode = "none";
+defparam \inst|reset_pin_in~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at LC_X25_Y42_N6
+stratix_lcell \inst|dly_counter_1_ (
+// Equation(s):
+// \inst|dly_counter [1] = DFFEAS(\reset~combout & (\inst|dly_counter [0] # \inst|dly_counter [1]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\reset~combout ),
+ .datac(\inst|dly_counter [0]),
+ .datad(\inst|dly_counter [1]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|dly_counter [1]),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|dly_counter_1_ .lut_mask = "ccc0";
+defparam \inst|dly_counter_1_ .operation_mode = "normal";
+defparam \inst|dly_counter_1_ .output_mode = "reg_only";
+defparam \inst|dly_counter_1_ .register_cascade_mode = "off";
+defparam \inst|dly_counter_1_ .sum_lutc_input = "datac";
+defparam \inst|dly_counter_1_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y41_N4
+stratix_lcell \inst|dly_counter_0_ (
+// Equation(s):
+// \inst|dly_counter [0] = DFFEAS(\reset~combout & (\inst|dly_counter [1] # !\inst|dly_counter [0]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\reset~combout ),
+ .datab(\inst|dly_counter [0]),
+ .datac(vcc),
+ .datad(\inst|dly_counter [1]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|dly_counter [0]),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|dly_counter_0_ .lut_mask = "aa22";
+defparam \inst|dly_counter_0_ .operation_mode = "normal";
+defparam \inst|dly_counter_0_ .output_mode = "reg_only";
+defparam \inst|dly_counter_0_ .register_cascade_mode = "off";
+defparam \inst|dly_counter_0_ .sum_lutc_input = "datac";
+defparam \inst|dly_counter_0_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X25_Y42_N0
+stratix_lcell \inst|vga_driver_unit|vsync_state_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|un6_dly_counter_0_x = !\inst|dly_counter [1] # !\inst|dly_counter [0] # !\reset~combout
+// \inst|vga_driver_unit|vsync_state_6 = DFFEAS(\inst|vga_driver_unit|un6_dly_counter_0_x , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\reset~combout ),
+ .datac(\inst|dly_counter [0]),
+ .datad(\inst|dly_counter [1]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .regout(\inst|vga_driver_unit|vsync_state_6 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_6_ .lut_mask = "3fff";
+defparam \inst|vga_driver_unit|vsync_state_6_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_6_ .output_mode = "reg_and_comb";
+defparam \inst|vga_driver_unit|vsync_state_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_6_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_6_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X18_Y42_N5
+stratix_lcell \inst|vga_driver_unit|hsync_state_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|d_set_hsync_counter = E1_hsync_state_6 # \inst|vga_driver_unit|hsync_state_0
+// \inst|vga_driver_unit|hsync_state_6 = DFFEAS(\inst|vga_driver_unit|d_set_hsync_counter , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|un6_dly_counter_0_x , , , VCC)
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .datad(\inst|vga_driver_unit|hsync_state_0 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|d_set_hsync_counter ),
+ .regout(\inst|vga_driver_unit|hsync_state_6 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_6_ .lut_mask = "fff0";
+defparam \inst|vga_driver_unit|hsync_state_6_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_6_ .output_mode = "reg_and_comb";
+defparam \inst|vga_driver_unit|hsync_state_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_6_ .sum_lutc_input = "qfbk";
+defparam \inst|vga_driver_unit|hsync_state_6_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N0
+stratix_lcell \inst|vga_driver_unit|hsync_counter_0_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_0 = DFFEAS(!\inst|vga_driver_unit|hsync_counter_0 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i ,
+// !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [0] = CARRY(\inst|vga_driver_unit|hsync_counter_0 )
+// \inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 = CARRY(\inst|vga_driver_unit|hsync_counter_0 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|hsync_counter_0 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_0 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [0]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_0_ .lut_mask = "33cc";
+defparam \inst|vga_driver_unit|hsync_counter_0_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_0_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_0_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_counter_0_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N1
+stratix_lcell \inst|vga_driver_unit|hsync_counter_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_1 = DFFEAS(\inst|vga_driver_unit|hsync_counter_1 $ \inst|vga_driver_unit|hsync_counter_cout [0], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [1] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [0] # !\inst|vga_driver_unit|hsync_counter_1 )
+// \inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 # !\inst|vga_driver_unit|hsync_counter_1 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|hsync_counter_1 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [0]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_1 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [1]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_1_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_1_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_1_ .lut_mask = "3c3f";
+defparam \inst|vga_driver_unit|hsync_counter_1_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_1_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_1_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_1_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N2
+stratix_lcell \inst|vga_driver_unit|hsync_counter_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_2 = DFFEAS(\inst|vga_driver_unit|hsync_counter_2 $ (!\inst|vga_driver_unit|hsync_counter_cout [1]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [2] = CARRY(\inst|vga_driver_unit|hsync_counter_2 & (!\inst|vga_driver_unit|hsync_counter_cout [1]))
+// \inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 = CARRY(\inst|vga_driver_unit|hsync_counter_2 & (!\inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 ))
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|hsync_counter_2 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [1]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_2 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [2]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_2_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_2_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_2_ .lut_mask = "a50a";
+defparam \inst|vga_driver_unit|hsync_counter_2_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_2_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_2_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_2_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N3
+stratix_lcell \inst|vga_driver_unit|hsync_counter_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_3 = DFFEAS(\inst|vga_driver_unit|hsync_counter_3 $ (\inst|vga_driver_unit|hsync_counter_cout [2]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [3] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [2] # !\inst|vga_driver_unit|hsync_counter_3 )
+// \inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 # !\inst|vga_driver_unit|hsync_counter_3 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|hsync_counter_3 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [2]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_3 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [3]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_3_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_3_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_3_ .lut_mask = "5a5f";
+defparam \inst|vga_driver_unit|hsync_counter_3_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_3_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_3_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_3_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N7
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 (
+// Equation(s):
+// \inst|vga_driver_unit|un13_hsync_counter_7 = \inst|vga_driver_unit|hsync_counter_1 & \inst|vga_driver_unit|hsync_counter_2 & \inst|vga_driver_unit|hsync_counter_3 & \inst|vga_driver_unit|hsync_counter_0
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_1 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_2 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_3 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_0 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un13_hsync_counter_7 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .lut_mask = "8000";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N4
+stratix_lcell \inst|vga_driver_unit|hsync_counter_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_4 = DFFEAS(\inst|vga_driver_unit|hsync_counter_4 $ (!\inst|vga_driver_unit|hsync_counter_cout [3]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [4] = CARRY(\inst|vga_driver_unit|hsync_counter_4 & (!\inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 ))
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|hsync_counter_4 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [3]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_4 ),
+ .cout(\inst|vga_driver_unit|hsync_counter_cout [4]),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_4_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_4_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_4_ .lut_mask = "a50a";
+defparam \inst|vga_driver_unit|hsync_counter_4_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_4_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_4_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_4_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N5
+stratix_lcell \inst|vga_driver_unit|hsync_counter_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_5 = DFFEAS(\inst|vga_driver_unit|hsync_counter_5 $ \inst|vga_driver_unit|hsync_counter_cout [4], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [5] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [4] # !\inst|vga_driver_unit|hsync_counter_5 )
+// \inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [4] # !\inst|vga_driver_unit|hsync_counter_5 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|hsync_counter_5 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|hsync_counter_cout [4]),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_5 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [5]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_5_ .cin_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_5_ .lut_mask = "3c3f";
+defparam \inst|vga_driver_unit|hsync_counter_5_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_5_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_5_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_5_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N6
+stratix_lcell \inst|vga_driver_unit|hsync_counter_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_6 = DFFEAS(\inst|vga_driver_unit|hsync_counter_6 $ !(!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [5]) # (\inst|vga_driver_unit|hsync_counter_cout [4] &
+// \inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [6] = CARRY(\inst|vga_driver_unit|hsync_counter_6 & !\inst|vga_driver_unit|hsync_counter_cout [5])
+// \inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 = CARRY(\inst|vga_driver_unit|hsync_counter_6 & !\inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|hsync_counter_6 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|hsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [5]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_6 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [6]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_6_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .cin_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .lut_mask = "c30c";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N7
+stratix_lcell \inst|vga_driver_unit|hsync_counter_7_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_7 = DFFEAS(\inst|vga_driver_unit|hsync_counter_7 $ ((!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [6]) # (\inst|vga_driver_unit|hsync_counter_cout [4] &
+// \inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [7] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [6] # !\inst|vga_driver_unit|hsync_counter_7 )
+// \inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 # !\inst|vga_driver_unit|hsync_counter_7 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|hsync_counter_7 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|hsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [6]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_7 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [7]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_7_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .cin_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .lut_mask = "5a5f";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N8
+stratix_lcell \inst|vga_driver_unit|hsync_counter_8_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_8 = DFFEAS(\inst|vga_driver_unit|hsync_counter_8 $ (!(!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [7]) # (\inst|vga_driver_unit|hsync_counter_cout [4] &
+// \inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [8] = CARRY(\inst|vga_driver_unit|hsync_counter_8 & (!\inst|vga_driver_unit|hsync_counter_cout [7]))
+// \inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 = CARRY(\inst|vga_driver_unit|hsync_counter_8 & (!\inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 ))
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|hsync_counter_8 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|hsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [7]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_8 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [8]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_8_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .cin_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .lut_mask = "a50a";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N9
+stratix_lcell \inst|vga_driver_unit|hsync_counter_9_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_9 = DFFEAS((!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [8]) # (\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 ) $
+// \inst|vga_driver_unit|hsync_counter_9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(\inst|vga_driver_unit|hsync_counter_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|hsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [8]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_9 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_9_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .cin_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .lut_mask = "0ff0";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N4
+stratix_lcell \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 (
+// Equation(s):
+// \inst|vga_driver_unit|un9_hsync_counterlt9_3 = !\inst|vga_driver_unit|hsync_counter_4 # !\inst|vga_driver_unit|hsync_counter_7 # !\inst|vga_driver_unit|hsync_counter_6 # !\inst|vga_driver_unit|hsync_counter_5
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_5 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_6 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_7 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_4 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un9_hsync_counterlt9_3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .lut_mask = "7fff";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N5
+stratix_lcell \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 (
+// Equation(s):
+// \inst|vga_driver_unit|un9_hsync_counterlt9 = \inst|vga_driver_unit|un9_hsync_counterlt9_3 # !\inst|vga_driver_unit|hsync_counter_8 # !\inst|vga_driver_unit|hsync_counter_9 # !\inst|vga_driver_unit|un13_hsync_counter_7
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un13_hsync_counter_7 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_9 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_8 ),
+ .datad(\inst|vga_driver_unit|un9_hsync_counterlt9_3 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .lut_mask = "ff7f";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N0
+stratix_lcell \inst|vga_driver_unit|G_2 (
+// Equation(s):
+// \inst|vga_driver_unit|G_2_i = !\inst|vga_driver_unit|hsync_state_6 & !\inst|vga_driver_unit|hsync_state_0 & !\inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|un9_hsync_counterlt9
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_state_6 ),
+ .datab(\inst|vga_driver_unit|hsync_state_0 ),
+ .datac(\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .datad(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|G_2_i ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|G_2 .lut_mask = "0f1f";
+defparam \inst|vga_driver_unit|G_2 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|G_2 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|G_2 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|G_2 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|G_2 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N1
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 (
+// Equation(s):
+// \inst|vga_driver_unit|un13_hsync_counter_2 = !\inst|vga_driver_unit|hsync_counter_5 & \inst|vga_driver_unit|hsync_counter_8 & \inst|vga_driver_unit|hsync_counter_9 & \inst|vga_driver_unit|hsync_counter_4
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_5 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_8 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_9 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_4 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un13_hsync_counter_2 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .lut_mask = "4000";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N6
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter (
+// Equation(s):
+// \inst|vga_driver_unit|un13_hsync_counter = !\inst|vga_driver_unit|hsync_counter_7 & \inst|vga_driver_unit|un13_hsync_counter_2 & \inst|vga_driver_unit|un13_hsync_counter_7 & !\inst|vga_driver_unit|hsync_counter_6
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_7 ),
+ .datab(\inst|vga_driver_unit|un13_hsync_counter_2 ),
+ .datac(\inst|vga_driver_unit|un13_hsync_counter_7 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un13_hsync_counter ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .lut_mask = "0040";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y43_N3
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 (
+// Equation(s):
+// \inst|vga_driver_unit|un11_hsync_counter_3 = !\inst|vga_driver_unit|hsync_counter_3 & \inst|vga_driver_unit|hsync_counter_0 & \inst|vga_driver_unit|hsync_counter_1 & !\inst|vga_driver_unit|hsync_counter_4
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_3 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_0 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_1 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_4 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un11_hsync_counter_3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .lut_mask = "0040";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y43_N6
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 (
+// Equation(s):
+// \inst|vga_driver_unit|un11_hsync_counter_2 = !\inst|vga_driver_unit|hsync_counter_6 & \inst|vga_driver_unit|hsync_counter_7 & \inst|vga_driver_unit|hsync_counter_2
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_6 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_7 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_2 ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un11_hsync_counter_2 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .lut_mask = "4040";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y43_N8
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_hsync_counter_1 = !\inst|vga_driver_unit|hsync_counter_9 & (!\inst|vga_driver_unit|hsync_counter_8 & !\inst|vga_driver_unit|hsync_counter_5 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_9 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_counter_8 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_hsync_counter_1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .lut_mask = "0005";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y43_N0
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_hsync_counter_4 = \inst|vga_driver_unit|hsync_counter_3 & \inst|vga_driver_unit|hsync_counter_1 & \inst|vga_driver_unit|hsync_counter_6 & \inst|vga_driver_unit|hsync_counter_4
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_3 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_1 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_6 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_4 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_hsync_counter_4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .lut_mask = "8000";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y43_N1
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_hsync_counter_3 = !\inst|vga_driver_unit|hsync_counter_7 & !\inst|vga_driver_unit|hsync_counter_2 & !\inst|vga_driver_unit|hsync_counter_0
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|hsync_counter_7 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_2 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_0 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_hsync_counter_3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .lut_mask = "0003";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X23_Y42_N2
+stratix_lcell \inst|vga_driver_unit|hsync_state_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_5 = DFFEAS(\inst|vga_driver_unit|hsync_state_0 # \inst|vga_driver_unit|hsync_state_6 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_state_0 ),
+ .datad(\inst|vga_driver_unit|hsync_state_6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_state_5 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_5_ .lut_mask = "fff0";
+defparam \inst|vga_driver_unit|hsync_state_5_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_5_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_state_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_5_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_5_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X22_Y43_N5
+stratix_lcell \inst|vga_driver_unit|hsync_state_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_4 = DFFEAS(\inst|vga_driver_unit|un10_hsync_counter_1 & \inst|vga_driver_unit|un10_hsync_counter_4 & \inst|vga_driver_unit|un10_hsync_counter_3 & \inst|vga_driver_unit|hsync_state_5 ,
+// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , , \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un10_hsync_counter_1 ),
+ .datab(\inst|vga_driver_unit|un10_hsync_counter_4 ),
+ .datac(\inst|vga_driver_unit|un10_hsync_counter_3 ),
+ .datad(\inst|vga_driver_unit|hsync_state_5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_state_4 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_4_ .lut_mask = "8000";
+defparam \inst|vga_driver_unit|hsync_state_4_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_4_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_state_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_4_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_4_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X22_Y43_N7
+stratix_lcell \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 = \inst|vga_driver_unit|hsync_state_4 & (!\inst|vga_driver_unit|un10_hsync_counter_1 # !\inst|vga_driver_unit|un11_hsync_counter_2 # !\inst|vga_driver_unit|un11_hsync_counter_3 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un11_hsync_counter_3 ),
+ .datab(\inst|vga_driver_unit|un11_hsync_counter_2 ),
+ .datac(\inst|vga_driver_unit|hsync_state_4 ),
+ .datad(\inst|vga_driver_unit|un10_hsync_counter_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .lut_mask = "70f0";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y43_N4
+stratix_lcell \inst|vga_driver_unit|hsync_state_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_1 = DFFEAS(\inst|vga_driver_unit|un11_hsync_counter_3 & \inst|vga_driver_unit|un11_hsync_counter_2 & \inst|vga_driver_unit|hsync_state_4 & \inst|vga_driver_unit|un10_hsync_counter_1 ,
+// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , , \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un11_hsync_counter_3 ),
+ .datab(\inst|vga_driver_unit|un11_hsync_counter_2 ),
+ .datac(\inst|vga_driver_unit|hsync_state_4 ),
+ .datad(\inst|vga_driver_unit|un10_hsync_counter_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_state_1 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_1_ .lut_mask = "8000";
+defparam \inst|vga_driver_unit|hsync_state_1_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_1_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_state_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_1_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N9
+stratix_lcell \inst|vga_driver_unit|hsync_state_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 = \inst|vga_driver_unit|un12_hsync_counter & !\inst|vga_driver_unit|un13_hsync_counter & (\inst|vga_driver_unit|hsync_state_2 ) # !\inst|vga_driver_unit|un12_hsync_counter & (E1_hsync_state_3 #
+// !\inst|vga_driver_unit|un13_hsync_counter & \inst|vga_driver_unit|hsync_state_2 )
+// \inst|vga_driver_unit|hsync_state_3 = DFFEAS(\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , \inst|vga_driver_unit|hsync_state_1 , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , VCC)
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un12_hsync_counter ),
+ .datab(\inst|vga_driver_unit|un13_hsync_counter ),
+ .datac(\inst|vga_driver_unit|hsync_state_1 ),
+ .datad(\inst|vga_driver_unit|hsync_state_2 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(vcc),
+ .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 ),
+ .regout(\inst|vga_driver_unit|hsync_state_3 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_3_ .lut_mask = "7350";
+defparam \inst|vga_driver_unit|hsync_state_3_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_3_ .output_mode = "reg_and_comb";
+defparam \inst|vga_driver_unit|hsync_state_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_3_ .sum_lutc_input = "qfbk";
+defparam \inst|vga_driver_unit|hsync_state_3_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N3
+stratix_lcell \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 = \inst|vga_driver_unit|hsync_state_5 & (!\inst|vga_driver_unit|un10_hsync_counter_3 # !\inst|vga_driver_unit|un10_hsync_counter_1 # !\inst|vga_driver_unit|un10_hsync_counter_4 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un10_hsync_counter_4 ),
+ .datab(\inst|vga_driver_unit|un10_hsync_counter_1 ),
+ .datac(\inst|vga_driver_unit|un10_hsync_counter_3 ),
+ .datad(\inst|vga_driver_unit|hsync_state_5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .lut_mask = "7f00";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N2
+stratix_lcell \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 & !\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 &
+// !\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 ),
+ .datab(\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 ),
+ .datac(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 ),
+ .datad(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .lut_mask = "ff01";
+defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X23_Y42_N9
+stratix_lcell \inst|vga_driver_unit|hsync_state_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_2 = DFFEAS(\inst|vga_driver_unit|hsync_state_3 & \inst|vga_driver_unit|un12_hsync_counter , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_state_3 ),
+ .datad(\inst|vga_driver_unit|un12_hsync_counter ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_state_2 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_2_ .lut_mask = "f000";
+defparam \inst|vga_driver_unit|hsync_state_2_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_2_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_state_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_2_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_2_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X23_Y42_N7
+stratix_lcell \inst|vga_driver_unit|hsync_state_0_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_0 = DFFEAS(\inst|vga_driver_unit|un13_hsync_counter & (\inst|vga_driver_unit|hsync_state_2 ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|un13_hsync_counter ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|hsync_state_2 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_state_0 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_0_ .lut_mask = "cc00";
+defparam \inst|vga_driver_unit|hsync_state_0_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_0_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_state_0_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_0_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X23_Y42_N3
+stratix_lcell \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa = \inst|dly_counter [0] & \inst|dly_counter [1] & \reset~combout & !\inst|vga_driver_unit|d_set_hsync_counter
+
+ .clk(gnd),
+ .dataa(\inst|dly_counter [0]),
+ .datab(\inst|dly_counter [1]),
+ .datac(\reset~combout ),
+ .datad(\inst|vga_driver_unit|d_set_hsync_counter ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .lut_mask = "0080";
+defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y43_N2
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 (
+// Equation(s):
+// \inst|vga_driver_unit|un12_hsync_counter_4 = !\inst|vga_driver_unit|hsync_counter_6 & !\inst|vga_driver_unit|hsync_counter_7 & \inst|vga_driver_unit|hsync_counter_2 & !\inst|vga_driver_unit|hsync_counter_4
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_6 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_7 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_2 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_4 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un12_hsync_counter_4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .lut_mask = "0010";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y43_N9
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 (
+// Equation(s):
+// \inst|vga_driver_unit|un12_hsync_counter_3 = \inst|vga_driver_unit|hsync_counter_9 & \inst|vga_driver_unit|hsync_counter_8 & !\inst|vga_driver_unit|hsync_counter_3 & !\inst|vga_driver_unit|hsync_counter_5
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_9 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_8 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_3 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un12_hsync_counter_3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .lut_mask = "0008";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N8
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter (
+// Equation(s):
+// \inst|vga_driver_unit|un12_hsync_counter = \inst|vga_driver_unit|hsync_counter_0 & \inst|vga_driver_unit|un12_hsync_counter_4 & \inst|vga_driver_unit|un12_hsync_counter_3 & \inst|vga_driver_unit|hsync_counter_1
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_0 ),
+ .datab(\inst|vga_driver_unit|un12_hsync_counter_4 ),
+ .datac(\inst|vga_driver_unit|un12_hsync_counter_3 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un12_hsync_counter ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .lut_mask = "8000";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X23_Y42_N4
+stratix_lcell \inst|vga_driver_unit|un1_hsync_state_3_0_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_hsync_state_3_0 = \inst|vga_driver_unit|hsync_state_3 # \inst|vga_driver_unit|hsync_state_1
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|hsync_state_3 ),
+ .datac(\inst|vga_driver_unit|hsync_state_1 ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_hsync_state_3_0 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .lut_mask = "fcfc";
+defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X23_Y42_N5
+stratix_lcell \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|h_sync_1_0_0_0_g1 = \inst|vga_driver_unit|un1_hsync_state_3_0 & (\inst|vga_driver_unit|h_sync ) # !\inst|vga_driver_unit|un1_hsync_state_3_0 & (\inst|vga_driver_unit|hsync_state_2 & (\inst|vga_driver_unit|h_sync ) #
+// !\inst|vga_driver_unit|hsync_state_2 & \inst|vga_driver_unit|hsync_state_4 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un1_hsync_state_3_0 ),
+ .datab(\inst|vga_driver_unit|hsync_state_2 ),
+ .datac(\inst|vga_driver_unit|hsync_state_4 ),
+ .datad(\inst|vga_driver_unit|h_sync ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|h_sync_1_0_0_0_g1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .lut_mask = "fe10";
+defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X23_Y42_N6
+stratix_lcell \inst|vga_driver_unit|h_sync_Z (
+// Equation(s):
+// \inst|vga_driver_unit|h_sync = DFFEAS(\inst|vga_driver_unit|h_sync_1_0_0_0_g1 # !\inst|dly_counter [1] # !\reset~combout # !\inst|dly_counter [0], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|dly_counter [0]),
+ .datab(\inst|vga_driver_unit|h_sync_1_0_0_0_g1 ),
+ .datac(\reset~combout ),
+ .datad(\inst|dly_counter [1]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|h_sync ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|h_sync_Z .lut_mask = "dfff";
+defparam \inst|vga_driver_unit|h_sync_Z .operation_mode = "normal";
+defparam \inst|vga_driver_unit|h_sync_Z .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|h_sync_Z .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|h_sync_Z .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|h_sync_Z .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X25_Y43_N0
+stratix_lcell \inst|vga_driver_unit|vsync_counter_0_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_0 = DFFEAS(\inst|vga_driver_unit|d_set_hsync_counter $ \inst|vga_driver_unit|vsync_counter_0 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [0] = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|vsync_counter_0 )
+// \inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|vsync_counter_0 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|d_set_hsync_counter ),
+ .datab(\inst|vga_driver_unit|vsync_counter_0 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_0 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [0]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_0_ .lut_mask = "6688";
+defparam \inst|vga_driver_unit|vsync_counter_0_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_0_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_0_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_counter_0_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y43_N1
+stratix_lcell \inst|vga_driver_unit|vsync_counter_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_1 = DFFEAS(\inst|vga_driver_unit|vsync_counter_1 $ \inst|vga_driver_unit|vsync_counter_cout [0], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [1] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [0] # !\inst|vga_driver_unit|vsync_counter_1 )
+// \inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 # !\inst|vga_driver_unit|vsync_counter_1 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|vsync_counter_1 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [0]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_1 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [1]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_1_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_1_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_1_ .lut_mask = "3c3f";
+defparam \inst|vga_driver_unit|vsync_counter_1_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_1_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_1_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_1_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y43_N2
+stratix_lcell \inst|vga_driver_unit|vsync_counter_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_2 = DFFEAS(\inst|vga_driver_unit|vsync_counter_2 $ (!\inst|vga_driver_unit|vsync_counter_cout [1]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [2] = CARRY(\inst|vga_driver_unit|vsync_counter_2 & (!\inst|vga_driver_unit|vsync_counter_cout [1]))
+// \inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 = CARRY(\inst|vga_driver_unit|vsync_counter_2 & (!\inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 ))
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_counter_2 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [1]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_2 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [2]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_2_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_2_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_2_ .lut_mask = "a50a";
+defparam \inst|vga_driver_unit|vsync_counter_2_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_2_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_2_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_2_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y43_N3
+stratix_lcell \inst|vga_driver_unit|vsync_counter_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_3 = DFFEAS(\inst|vga_driver_unit|vsync_counter_3 $ (\inst|vga_driver_unit|vsync_counter_cout [2]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [3] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [2] # !\inst|vga_driver_unit|vsync_counter_3 )
+// \inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 # !\inst|vga_driver_unit|vsync_counter_3 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_counter_3 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [2]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_3 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [3]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_3_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_3_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_3_ .lut_mask = "5a5f";
+defparam \inst|vga_driver_unit|vsync_counter_3_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_3_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_3_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_3_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y42_N3
+stratix_lcell \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 (
+// Equation(s):
+// \inst|vga_driver_unit|un9_vsync_counterlt9_6 = !\inst|vga_driver_unit|vsync_counter_3 # !\inst|vga_driver_unit|vsync_counter_1 # !\inst|vga_driver_unit|vsync_counter_2 # !\inst|vga_driver_unit|vsync_counter_0
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_0 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_2 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_1 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_3 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un9_vsync_counterlt9_6 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .lut_mask = "7fff";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X25_Y43_N4
+stratix_lcell \inst|vga_driver_unit|vsync_counter_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_4 = DFFEAS(\inst|vga_driver_unit|vsync_counter_4 $ (!\inst|vga_driver_unit|vsync_counter_cout [3]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [4] = CARRY(\inst|vga_driver_unit|vsync_counter_4 & (!\inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 ))
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_counter_4 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [3]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_4 ),
+ .cout(\inst|vga_driver_unit|vsync_counter_cout [4]),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_4_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_4_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_4_ .lut_mask = "a50a";
+defparam \inst|vga_driver_unit|vsync_counter_4_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_4_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_4_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_4_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y43_N5
+stratix_lcell \inst|vga_driver_unit|vsync_counter_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_5 = DFFEAS(\inst|vga_driver_unit|vsync_counter_5 $ \inst|vga_driver_unit|vsync_counter_cout [4], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [5] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [4] # !\inst|vga_driver_unit|vsync_counter_5 )
+// \inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [4] # !\inst|vga_driver_unit|vsync_counter_5 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|vsync_counter_5 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|vsync_counter_cout [4]),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_5 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [5]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_5_ .cin_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_5_ .lut_mask = "3c3f";
+defparam \inst|vga_driver_unit|vsync_counter_5_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_5_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_5_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_5_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y43_N6
+stratix_lcell \inst|vga_driver_unit|vsync_counter_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_6 = DFFEAS(\inst|vga_driver_unit|vsync_counter_6 $ !(!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [5]) # (\inst|vga_driver_unit|vsync_counter_cout [4] &
+// \inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [6] = CARRY(\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_cout [5])
+// \inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 = CARRY(\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|vsync_counter_6 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|vsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [5]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_6 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [6]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_6_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .cin_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .lut_mask = "c30c";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y43_N7
+stratix_lcell \inst|vga_driver_unit|vsync_counter_7_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_7 = DFFEAS(\inst|vga_driver_unit|vsync_counter_7 $ ((!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [6]) # (\inst|vga_driver_unit|vsync_counter_cout [4] &
+// \inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [7] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [6] # !\inst|vga_driver_unit|vsync_counter_7 )
+// \inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 # !\inst|vga_driver_unit|vsync_counter_7 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_counter_7 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|vsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [6]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_7 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [7]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_7_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .cin_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .lut_mask = "5a5f";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y43_N8
+stratix_lcell \inst|vga_driver_unit|vsync_counter_8_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_8 = DFFEAS(\inst|vga_driver_unit|vsync_counter_8 $ (!(!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [7]) # (\inst|vga_driver_unit|vsync_counter_cout [4] &
+// \inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [8] = CARRY(\inst|vga_driver_unit|vsync_counter_8 & (!\inst|vga_driver_unit|vsync_counter_cout [7]))
+// \inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 = CARRY(\inst|vga_driver_unit|vsync_counter_8 & (!\inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 ))
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_counter_8 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|vsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [7]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_8 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [8]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_8_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .cin_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .lut_mask = "a50a";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y43_N9
+stratix_lcell \inst|vga_driver_unit|vsync_counter_9_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_9 = DFFEAS((!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [8]) # (\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 ) $
+// \inst|vga_driver_unit|vsync_counter_9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(\inst|vga_driver_unit|vsync_counter_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|vsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [8]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_9 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_9_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .cin_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .lut_mask = "0ff0";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y42_N7
+stratix_lcell \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 (
+// Equation(s):
+// \inst|vga_driver_unit|un9_vsync_counterlt9_5 = !\inst|vga_driver_unit|vsync_counter_8 # !\inst|vga_driver_unit|vsync_counter_7 # !\inst|vga_driver_unit|vsync_counter_6 # !\inst|vga_driver_unit|vsync_counter_9
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_9 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_6 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_7 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un9_vsync_counterlt9_5 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .lut_mask = "7fff";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X25_Y42_N5
+stratix_lcell \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 (
+// Equation(s):
+// \inst|vga_driver_unit|un9_vsync_counterlt9 = \inst|vga_driver_unit|un9_vsync_counterlt9_6 # \inst|vga_driver_unit|un9_vsync_counterlt9_5 # !\inst|vga_driver_unit|vsync_counter_5 # !\inst|vga_driver_unit|vsync_counter_4
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un9_vsync_counterlt9_6 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_4 ),
+ .datac(\inst|vga_driver_unit|un9_vsync_counterlt9_5 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .lut_mask = "fbff";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X25_Y42_N2
+stratix_lcell \inst|vga_driver_unit|G_16 (
+// Equation(s):
+// \inst|vga_driver_unit|G_16_i = !\inst|vga_driver_unit|vsync_state_0 & !\inst|vga_driver_unit|un6_dly_counter_0_x & !\inst|vga_driver_unit|vsync_state_6 # !\inst|vga_driver_unit|un9_vsync_counterlt9
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_state_0 ),
+ .datab(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .datac(\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .datad(\inst|vga_driver_unit|vsync_state_6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|G_16_i ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|G_16 .lut_mask = "0f1f";
+defparam \inst|vga_driver_unit|G_16 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|G_16 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|G_16 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|G_16 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|G_16 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y42_N4
+stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 (
+// Equation(s):
+// \inst|vga_driver_unit|un12_vsync_counter_7 = !\inst|vga_driver_unit|vsync_counter_4 & !\inst|vga_driver_unit|vsync_counter_1 & !\inst|vga_driver_unit|vsync_counter_2 & !\inst|vga_driver_unit|vsync_counter_3
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_4 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_1 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_2 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_3 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un12_vsync_counter_7 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .lut_mask = "0001";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y42_N2
+stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 (
+// Equation(s):
+// \inst|vga_driver_unit|un12_vsync_counter_6 = !\inst|vga_driver_unit|vsync_counter_5 & !\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_7 & !\inst|vga_driver_unit|vsync_counter_8
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_5 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_6 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_7 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un12_vsync_counter_6 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .lut_mask = "0001";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y42_N1
+stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 (
+// Equation(s):
+// \inst|vga_driver_unit|un14_vsync_counter_8 = \inst|vga_driver_unit|un12_vsync_counter_7 & (\inst|vga_driver_unit|un12_vsync_counter_6 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un12_vsync_counter_7 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un12_vsync_counter_6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un14_vsync_counter_8 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .lut_mask = "aa00";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y41_N8
+stratix_lcell \inst|vga_driver_unit|vsync_state_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_5 = DFFEAS(\inst|vga_driver_unit|vsync_state_0 # \inst|vga_driver_unit|vsync_state_6 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|vsync_state_0 ),
+ .datac(\inst|vga_driver_unit|vsync_state_6 ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_state_5 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_5_ .lut_mask = "fcfc";
+defparam \inst|vga_driver_unit|vsync_state_5_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_5_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_state_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_5_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_5_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X24_Y42_N8
+stratix_lcell \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 = \inst|vga_driver_unit|vsync_state_5 & (\inst|vga_driver_unit|vsync_counter_9 # !\inst|vga_driver_unit|un14_vsync_counter_8 # !\inst|vga_driver_unit|vsync_counter_0 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_0 ),
+ .datab(\inst|vga_driver_unit|un14_vsync_counter_8 ),
+ .datac(\inst|vga_driver_unit|vsync_state_5 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .lut_mask = "f070";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y41_N6
+stratix_lcell \inst|vga_driver_unit|vsync_state_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_4 = DFFEAS(\inst|vga_driver_unit|vsync_state_5 & \inst|vga_driver_unit|un14_vsync_counter_8 & \inst|vga_driver_unit|vsync_counter_0 & !\inst|vga_driver_unit|vsync_counter_9 , GLOBAL(\inst1|altpll_component|_clk0 ),
+// VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , , , \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_state_5 ),
+ .datab(\inst|vga_driver_unit|un14_vsync_counter_8 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_0 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_state_4 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_4_ .lut_mask = "0080";
+defparam \inst|vga_driver_unit|vsync_state_4_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_4_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_state_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_4_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_4_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y42_N4
+stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 (
+// Equation(s):
+// \inst|vga_driver_unit|un13_vsync_counter_3 = !\inst|vga_driver_unit|vsync_counter_9 & !\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_7 & !\inst|vga_driver_unit|vsync_counter_8
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_9 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_6 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_7 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un13_vsync_counter_3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .lut_mask = "0001";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y42_N3
+stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 (
+// Equation(s):
+// \inst|vga_driver_unit|un13_vsync_counter_4 = \inst|vga_driver_unit|vsync_counter_5 & \inst|vga_driver_unit|un13_vsync_counter_3 & \inst|vga_driver_unit|vsync_counter_0
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_5 ),
+ .datab(\inst|vga_driver_unit|un13_vsync_counter_3 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_0 ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un13_vsync_counter_4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .lut_mask = "8080";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y41_N3
+stratix_lcell \inst|vga_driver_unit|vsync_state_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_1 = DFFEAS(\inst|vga_driver_unit|un12_vsync_counter_7 & \inst|vga_driver_unit|vsync_state_4 & \inst|vga_driver_unit|un13_vsync_counter_4 & !\inst|vga_driver_unit|un6_dly_counter_0_x ,
+// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un12_vsync_counter_7 ),
+ .datab(\inst|vga_driver_unit|vsync_state_4 ),
+ .datac(\inst|vga_driver_unit|un13_vsync_counter_4 ),
+ .datad(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_state_1 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_1_ .lut_mask = "0080";
+defparam \inst|vga_driver_unit|vsync_state_1_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_1_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_state_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_1_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y42_N6
+stratix_lcell \inst|vga_driver_unit|vsync_state_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 = E1_vsync_state_3 & (!\inst|vga_driver_unit|vsync_counter_9 # !\inst|vga_driver_unit|un14_vsync_counter_8 # !\inst|vga_driver_unit|vsync_counter_0 )
+// \inst|vga_driver_unit|vsync_state_3 = DFFEAS(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , \inst|vga_driver_unit|vsync_state_1 , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , VCC)
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_counter_0 ),
+ .datab(\inst|vga_driver_unit|un14_vsync_counter_8 ),
+ .datac(\inst|vga_driver_unit|vsync_state_1 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(vcc),
+ .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 ),
+ .regout(\inst|vga_driver_unit|vsync_state_3 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_3_ .lut_mask = "70f0";
+defparam \inst|vga_driver_unit|vsync_state_3_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_3_ .output_mode = "reg_and_comb";
+defparam \inst|vga_driver_unit|vsync_state_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_3_ .sum_lutc_input = "qfbk";
+defparam \inst|vga_driver_unit|vsync_state_3_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X24_Y42_N5
+stratix_lcell \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 = \inst|vga_driver_unit|vsync_state_4 & (!\inst|vga_driver_unit|un12_vsync_counter_7 # !\inst|vga_driver_unit|un13_vsync_counter_4 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_state_4 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un13_vsync_counter_4 ),
+ .datad(\inst|vga_driver_unit|un12_vsync_counter_7 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .lut_mask = "0aaa";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y43_N5
+stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 (
+// Equation(s):
+// \inst|vga_driver_unit|un15_vsync_counter_3 = \inst|vga_driver_unit|vsync_counter_3 & !\inst|vga_driver_unit|vsync_counter_2 & !\inst|vga_driver_unit|vsync_counter_0 & \inst|vga_driver_unit|vsync_counter_9
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_3 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_2 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_0 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un15_vsync_counter_3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .lut_mask = "0200";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y43_N2
+stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 (
+// Equation(s):
+// \inst|vga_driver_unit|un15_vsync_counter_4 = \inst|vga_driver_unit|un15_vsync_counter_3 & !\inst|vga_driver_unit|vsync_counter_4 & !\inst|vga_driver_unit|vsync_counter_1
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|un15_vsync_counter_3 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_4 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un15_vsync_counter_4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .lut_mask = "000c";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y42_N9
+stratix_lcell \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 = \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 # \inst|vga_driver_unit|vsync_state_2 & (!\inst|vga_driver_unit|un15_vsync_counter_4 # !\inst|vga_driver_unit|un12_vsync_counter_6 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un12_vsync_counter_6 ),
+ .datab(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 ),
+ .datac(\inst|vga_driver_unit|vsync_state_2 ),
+ .datad(\inst|vga_driver_unit|un15_vsync_counter_4 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .lut_mask = "dcfc";
+defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y42_N7
+stratix_lcell \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_next_2_sqmuxa = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 & !\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 &
+// !\inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 ),
+ .datab(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 ),
+ .datac(\inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 ),
+ .datad(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .lut_mask = "ff01";
+defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y43_N4
+stratix_lcell \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 = \inst|vga_driver_unit|un12_vsync_counter_6 & \inst|vga_driver_unit|vsync_state_2 & \inst|vga_driver_unit|un15_vsync_counter_4
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|un12_vsync_counter_6 ),
+ .datac(\inst|vga_driver_unit|vsync_state_2 ),
+ .datad(\inst|vga_driver_unit|un15_vsync_counter_4 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .lut_mask = "c000";
+defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y42_N0
+stratix_lcell \inst|vga_driver_unit|vsync_state_0_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_0 = DFFEAS(\inst|vga_driver_unit|un6_dly_counter_0_x & \inst|vga_driver_unit|vsync_state_0 & !\inst|vga_driver_unit|vsync_state_next_2_sqmuxa # !\inst|vga_driver_unit|un6_dly_counter_0_x &
+// (\inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 # \inst|vga_driver_unit|vsync_state_0 & !\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .datab(\inst|vga_driver_unit|vsync_state_0 ),
+ .datac(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ),
+ .datad(\inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_state_0 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_0_ .lut_mask = "5d0c";
+defparam \inst|vga_driver_unit|vsync_state_0_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_0_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_state_0_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_0_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X25_Y42_N9
+stratix_lcell \inst|vga_driver_unit|d_set_vsync_counter_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|d_set_vsync_counter = \inst|vga_driver_unit|vsync_state_0 # \inst|vga_driver_unit|vsync_state_6
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_state_0 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|vsync_state_6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|d_set_vsync_counter ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .lut_mask = "ffaa";
+defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X25_Y42_N8
+stratix_lcell \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa = \inst|dly_counter [1] & !\inst|vga_driver_unit|d_set_vsync_counter & \inst|dly_counter [0] & \reset~combout
+
+ .clk(gnd),
+ .dataa(\inst|dly_counter [1]),
+ .datab(\inst|vga_driver_unit|d_set_vsync_counter ),
+ .datac(\inst|dly_counter [0]),
+ .datad(\reset~combout ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .lut_mask = "2000";
+defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y41_N0
+stratix_lcell \inst|vga_driver_unit|vsync_state_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_2 = DFFEAS(\inst|vga_driver_unit|vsync_counter_0 & \inst|vga_driver_unit|vsync_state_3 & \inst|vga_driver_unit|un14_vsync_counter_8 & \inst|vga_driver_unit|vsync_counter_9 , GLOBAL(\inst1|altpll_component|_clk0 ),
+// VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , , , \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_counter_0 ),
+ .datab(\inst|vga_driver_unit|vsync_state_3 ),
+ .datac(\inst|vga_driver_unit|un14_vsync_counter_8 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_state_2 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_2_ .lut_mask = "8000";
+defparam \inst|vga_driver_unit|vsync_state_2_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_2_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_state_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_2_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_2_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X24_Y41_N7
+stratix_lcell \inst|vga_driver_unit|un1_vsync_state_2_0_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_vsync_state_2_0 = \inst|vga_driver_unit|vsync_state_3 # \inst|vga_driver_unit|vsync_state_1
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|vsync_state_3 ),
+ .datac(\inst|vga_driver_unit|vsync_state_1 ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_vsync_state_2_0 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .lut_mask = "fcfc";
+defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y41_N5
+stratix_lcell \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|v_sync_1_0_0_0_g1 = \inst|vga_driver_unit|vsync_state_2 & (\inst|vga_driver_unit|v_sync ) # !\inst|vga_driver_unit|vsync_state_2 & (\inst|vga_driver_unit|un1_vsync_state_2_0 & (\inst|vga_driver_unit|v_sync ) #
+// !\inst|vga_driver_unit|un1_vsync_state_2_0 & \inst|vga_driver_unit|vsync_state_4 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_state_2 ),
+ .datab(\inst|vga_driver_unit|vsync_state_4 ),
+ .datac(\inst|vga_driver_unit|un1_vsync_state_2_0 ),
+ .datad(\inst|vga_driver_unit|v_sync ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|v_sync_1_0_0_0_g1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .lut_mask = "fe04";
+defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y41_N9
+stratix_lcell \inst|vga_driver_unit|v_sync_Z (
+// Equation(s):
+// \inst|vga_driver_unit|v_sync = DFFEAS(\inst|vga_driver_unit|v_sync_1_0_0_0_g1 # !\inst|dly_counter [1] # !\inst|dly_counter [0] # !\reset~combout , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\reset~combout ),
+ .datab(\inst|dly_counter [0]),
+ .datac(\inst|vga_driver_unit|v_sync_1_0_0_0_g1 ),
+ .datad(\inst|dly_counter [1]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|v_sync ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|v_sync_Z .lut_mask = "f7ff";
+defparam \inst|vga_driver_unit|v_sync_Z .operation_mode = "normal";
+defparam \inst|vga_driver_unit|v_sync_Z .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|v_sync_Z .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|v_sync_Z .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|v_sync_Z .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X51_Y30_N5
+stratix_lcell \~STRATIX_FITTER_CREATED_GND~I (
+// Equation(s):
+// \~STRATIX_FITTER_CREATED_GND~I_combout = GND
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \~STRATIX_FITTER_CREATED_GND~I .lut_mask = "0000";
+defparam \~STRATIX_FITTER_CREATED_GND~I .operation_mode = "normal";
+defparam \~STRATIX_FITTER_CREATED_GND~I .output_mode = "comb_only";
+defparam \~STRATIX_FITTER_CREATED_GND~I .register_cascade_mode = "off";
+defparam \~STRATIX_FITTER_CREATED_GND~I .sum_lutc_input = "datac";
+defparam \~STRATIX_FITTER_CREATED_GND~I .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X25_Y42_N1
+stratix_lcell \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 = \inst|dly_counter [0] & \reset~combout & !\inst|vga_driver_unit|hsync_state_1 & \inst|dly_counter [1]
+
+ .clk(gnd),
+ .dataa(\inst|dly_counter [0]),
+ .datab(\reset~combout ),
+ .datac(\inst|vga_driver_unit|hsync_state_1 ),
+ .datad(\inst|dly_counter [1]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .lut_mask = "0800";
+defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y32_N4
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_0_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_0 = DFFEAS(!\inst|vga_driver_unit|column_counter_sig_0 # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datad(\inst|vga_driver_unit|column_counter_sig_0 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_0 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_0_ .lut_mask = "0fff";
+defparam \inst|vga_driver_unit|column_counter_sig_0_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_0_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_0_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_0_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X48_Y33_N0
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [1] = \inst|vga_driver_unit|column_counter_sig_0 $ \inst|vga_driver_unit|column_counter_sig_1
+// \inst|vga_driver_unit|un2_column_counter_next_cout [1] = CARRY(\inst|vga_driver_unit|column_counter_sig_0 & \inst|vga_driver_unit|column_counter_sig_1 )
+// \inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 = CARRY(\inst|vga_driver_unit|column_counter_sig_0 & \inst|vga_driver_unit|column_counter_sig_1 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_0 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_1 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [1]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [1]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .lut_mask = "6688";
+defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y33_N5
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_1 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [1] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [1]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_1 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_1_ .lut_mask = "ff55";
+defparam \inst|vga_driver_unit|column_counter_sig_1_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_1_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_1_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X48_Y33_N1
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [3] = \inst|vga_driver_unit|column_counter_sig_3 $ (\inst|vga_driver_unit|column_counter_sig_2 & \inst|vga_driver_unit|un2_column_counter_next_cout [1])
+// \inst|vga_driver_unit|un2_column_counter_next_cout [3] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [1] # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_2 )
+// \inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_2 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_2 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_3 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [1]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [3]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [3]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .lut_mask = "6c7f";
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y32_N2
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_3 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [3] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [3]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_3 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_3_ .lut_mask = "ff0f";
+defparam \inst|vga_driver_unit|column_counter_sig_3_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_3_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_3_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_3_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X49_Y32_N0
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_0_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_cout [0] = CARRY(\inst|vga_driver_unit|column_counter_sig_0 & \inst|vga_driver_unit|column_counter_sig_1 )
+// \inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 = CARRY(\inst|vga_driver_unit|column_counter_sig_0 & \inst|vga_driver_unit|column_counter_sig_1 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_0 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_1 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_0_~COMBOUT ),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [0]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .lut_mask = "ff88";
+defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .output_mode = "none";
+defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X49_Y32_N1
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [2] = \inst|vga_driver_unit|column_counter_sig_2 $ (\inst|vga_driver_unit|un2_column_counter_next_cout [0])
+// \inst|vga_driver_unit|un2_column_counter_next_cout [2] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [0] # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_2 )
+// \inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_2 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_2 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_3 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [0]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [2]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [2]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .lut_mask = "5a7f";
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X49_Y32_N2
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [4] = \inst|vga_driver_unit|column_counter_sig_4 $ !\inst|vga_driver_unit|un2_column_counter_next_cout [2]
+// \inst|vga_driver_unit|un2_column_counter_next_cout [4] = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout [2])
+// \inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_5 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_4 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [2]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [4]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [4]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .lut_mask = "c308";
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y32_N8
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_4 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [4] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [4]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_4 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_4_ .lut_mask = "ff0f";
+defparam \inst|vga_driver_unit|column_counter_sig_4_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_4_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_4_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_4_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X48_Y33_N2
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [5] = \inst|vga_driver_unit|column_counter_sig_5 $ (\inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout [3])
+// \inst|vga_driver_unit|un2_column_counter_next_cout [5] = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout [3])
+// \inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_5 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_4 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [3]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [5]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [5]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .lut_mask = "a608";
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y32_N9
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_5 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [5] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datac(\inst|vga_driver_unit|un2_column_counter_next_combout [5]),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_5 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_5_ .lut_mask = "f3f3";
+defparam \inst|vga_driver_unit|column_counter_sig_5_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_5_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_5_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_5_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X49_Y32_N3
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [6] = \inst|vga_driver_unit|column_counter_sig_6 $ \inst|vga_driver_unit|un2_column_counter_next_cout [4]
+// \inst|vga_driver_unit|un2_column_counter_next_cout [6] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [4] # !\inst|vga_driver_unit|column_counter_sig_6 # !\inst|vga_driver_unit|column_counter_sig_7 )
+// \inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 # !\inst|vga_driver_unit|column_counter_sig_6 # !\inst|vga_driver_unit|column_counter_sig_7 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_7 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_6 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [4]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [6]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [6]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .lut_mask = "3c7f";
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y32_N6
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_6 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [6] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [6]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_6 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_6_ .lut_mask = "ff0f";
+defparam \inst|vga_driver_unit|column_counter_sig_6_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_6_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_6_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_6_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X48_Y33_N3
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_7_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [7] = \inst|vga_driver_unit|column_counter_sig_7 $ (\inst|vga_driver_unit|column_counter_sig_6 & \inst|vga_driver_unit|un2_column_counter_next_cout [5])
+// \inst|vga_driver_unit|un2_column_counter_next_cout [7] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [5] # !\inst|vga_driver_unit|column_counter_sig_7 # !\inst|vga_driver_unit|column_counter_sig_6 )
+// \inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 # !\inst|vga_driver_unit|column_counter_sig_7 # !\inst|vga_driver_unit|column_counter_sig_6 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_6 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_7 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [5]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [7]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [7]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .lut_mask = "6c7f";
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y33_N8
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_7_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_7 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [7] & (\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 & \inst|vga_driver_unit|un10_column_counter_siglto9 ),
+// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un2_column_counter_next_combout [7]),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .datad(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_7 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_7_ .lut_mask = "a000";
+defparam \inst|vga_driver_unit|column_counter_sig_7_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_7_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_7_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_7_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_7_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X49_Y32_N4
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_8_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [8] = \inst|vga_driver_unit|column_counter_sig_8 $ !\inst|vga_driver_unit|un2_column_counter_next_cout [6]
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|column_counter_sig_8 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [6]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [8]),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .lut_mask = "c3c3";
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y33_N7
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_8_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_8 = DFFEAS(\inst|vga_driver_unit|un10_column_counter_siglto9 & (\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 & \inst|vga_driver_unit|un2_column_counter_next_combout [8]),
+// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [8]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_8 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_8_ .lut_mask = "a000";
+defparam \inst|vga_driver_unit|column_counter_sig_8_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_8_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_8_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_8_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_8_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y33_N4
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_9_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [9] = \inst|vga_driver_unit|column_counter_sig_9 $ (\inst|vga_driver_unit|column_counter_sig_8 & !\inst|vga_driver_unit|un2_column_counter_next_cout [7])
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_8 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|column_counter_sig_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [7]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [9]),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .lut_mask = "f50a";
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y33_N9
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_9_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_9 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [9] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [9]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_9 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_9_ .lut_mask = "ff55";
+defparam \inst|vga_driver_unit|column_counter_sig_9_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_9_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_9_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_9_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_9_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X48_Y32_N0
+stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_2 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_column_counter_siglt6_2 = !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_4 # !\inst|vga_driver_unit|column_counter_sig_2
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_2 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|column_counter_sig_4 ),
+ .datad(\inst|vga_driver_unit|column_counter_sig_3 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_column_counter_siglt6_2 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_2 .lut_mask = "5fff";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_2 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_2 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_2 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_2 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_2 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y32_N3
+stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_column_counter_siglt6_1 = !\inst|vga_driver_unit|column_counter_sig_6 # !\inst|vga_driver_unit|column_counter_sig_5
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|column_counter_sig_5 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|column_counter_sig_6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_column_counter_siglt6_1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .lut_mask = "33ff";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y32_N7
+stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_column_counter_siglt6 = \inst|vga_driver_unit|un10_column_counter_siglt6_2 # \inst|vga_driver_unit|un10_column_counter_siglt6_1 # !\inst|vga_driver_unit|column_counter_sig_1 # !\inst|vga_driver_unit|column_counter_sig_0
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_0 ),
+ .datab(\inst|vga_driver_unit|un10_column_counter_siglt6_2 ),
+ .datac(\inst|vga_driver_unit|un10_column_counter_siglt6_1 ),
+ .datad(\inst|vga_driver_unit|column_counter_sig_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_column_counter_siglt6 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .lut_mask = "fdff";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y32_N5
+stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_column_counter_siglto9 = !\inst|vga_driver_unit|column_counter_sig_7 & \inst|vga_driver_unit|un10_column_counter_siglt6 & !\inst|vga_driver_unit|column_counter_sig_8 # !\inst|vga_driver_unit|column_counter_sig_9
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_9 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_7 ),
+ .datac(\inst|vga_driver_unit|un10_column_counter_siglt6 ),
+ .datad(\inst|vga_driver_unit|column_counter_sig_8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .lut_mask = "5575";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y32_N1
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_2 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [2] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [2]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_2 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_2_ .lut_mask = "ff0f";
+defparam \inst|vga_driver_unit|column_counter_sig_2_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_2_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_2_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_2_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X49_Y33_N4
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto3 (
+// Equation(s):
+// \inst|vga_control_unit|un5_v_enablelto3 = \inst|vga_driver_unit|column_counter_sig_3 & (\inst|vga_driver_unit|column_counter_sig_2 # \inst|vga_driver_unit|column_counter_sig_0 # \inst|vga_driver_unit|column_counter_sig_1 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_2 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_3 ),
+ .datac(\inst|vga_driver_unit|column_counter_sig_0 ),
+ .datad(\inst|vga_driver_unit|column_counter_sig_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un5_v_enablelto3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto3 .lut_mask = "ccc8";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto3 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto3 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto3 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto3 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto3 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X48_Y33_N6
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5_0 (
+// Equation(s):
+// \inst|vga_control_unit|un5_v_enablelto5_0 = \inst|vga_driver_unit|column_counter_sig_4 # \inst|vga_driver_unit|column_counter_sig_5
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|column_counter_sig_4 ),
+ .datac(\inst|vga_driver_unit|column_counter_sig_5 ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un5_v_enablelto5_0 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5_0 .lut_mask = "fcfc";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5_0 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5_0 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5_0 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5_0 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5_0 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X49_Y33_N2
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto7 (
+// Equation(s):
+// \inst|vga_control_unit|un5_v_enablelto7 = \inst|vga_driver_unit|column_counter_sig_7 & \inst|vga_driver_unit|column_counter_sig_6 & (\inst|vga_control_unit|un5_v_enablelto3 # \inst|vga_control_unit|un5_v_enablelto5_0 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|un5_v_enablelto3 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_7 ),
+ .datac(\inst|vga_driver_unit|column_counter_sig_6 ),
+ .datad(\inst|vga_control_unit|un5_v_enablelto5_0 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un5_v_enablelto7 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto7 .lut_mask = "c080";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto7 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto7 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto7 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto7 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto7 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X1_Y33_N5
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [1] = \inst|vga_driver_unit|line_counter_sig_0 $ \inst|vga_driver_unit|d_set_hsync_counter
+// \inst|vga_driver_unit|un1_line_counter_sig_cout [1] = CARRY(\inst|vga_driver_unit|line_counter_sig_0 & \inst|vga_driver_unit|d_set_hsync_counter )
+// \inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 = CARRY(\inst|vga_driver_unit|line_counter_sig_0 & \inst|vga_driver_unit|d_set_hsync_counter )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_0 ),
+ .datab(\inst|vga_driver_unit|d_set_hsync_counter ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [1]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [1]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .lut_mask = "6688";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y41_N2
+stratix_lcell \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 = \reset~combout & \inst|dly_counter [0] & !\inst|vga_driver_unit|vsync_state_1 & \inst|dly_counter [1]
+
+ .clk(gnd),
+ .dataa(\reset~combout ),
+ .datab(\inst|dly_counter [0]),
+ .datac(\inst|vga_driver_unit|vsync_state_1 ),
+ .datad(\inst|dly_counter [1]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .lut_mask = "0800";
+defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X1_Y33_N4
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_0_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_0 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [1] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .datac(\inst|vga_driver_unit|un1_line_counter_sig_combout [1]),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_0 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_0_ .lut_mask = "f3f3";
+defparam \inst|vga_driver_unit|line_counter_sig_0_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_0_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_0_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_0_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X1_Y33_N6
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [3] = \inst|vga_driver_unit|line_counter_sig_2 $ (\inst|vga_driver_unit|line_counter_sig_1 & \inst|vga_driver_unit|un1_line_counter_sig_cout [1])
+// \inst|vga_driver_unit|un1_line_counter_sig_cout [3] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout [1] # !\inst|vga_driver_unit|line_counter_sig_1 # !\inst|vga_driver_unit|line_counter_sig_2 )
+// \inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 # !\inst|vga_driver_unit|line_counter_sig_1 # !\inst|vga_driver_unit|line_counter_sig_2 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_2 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_1 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [1]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [3]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [3]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .lut_mask = "6a7f";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X1_Y33_N3
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_2 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [3] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .datad(\inst|vga_driver_unit|un1_line_counter_sig_combout [3]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_2 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_2_ .lut_mask = "ff0f";
+defparam \inst|vga_driver_unit|line_counter_sig_2_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_2_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_2_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_2_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X2_Y33_N0
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_a_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_a_cout [1] = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|line_counter_sig_0 )
+// \inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|line_counter_sig_0 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|d_set_hsync_counter ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_0 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT ),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .lut_mask = "ff88";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .output_mode = "none";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X2_Y33_N1
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [2] = \inst|vga_driver_unit|line_counter_sig_1 $ (\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1])
+// \inst|vga_driver_unit|un1_line_counter_sig_cout [2] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1] # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 )
+// \inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_1 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_2 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [2]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [2]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .lut_mask = "5a7f";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X3_Y33_N4
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_1 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [2] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un1_line_counter_sig_combout [2]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_1 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_1_ .lut_mask = "ff33";
+defparam \inst|vga_driver_unit|line_counter_sig_1_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_1_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_1_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X2_Y33_N2
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [4] = \inst|vga_driver_unit|line_counter_sig_3 $ !\inst|vga_driver_unit|un1_line_counter_sig_cout [2]
+// \inst|vga_driver_unit|un1_line_counter_sig_cout [4] = CARRY(\inst|vga_driver_unit|line_counter_sig_4 & \inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout [2])
+// \inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 = CARRY(\inst|vga_driver_unit|line_counter_sig_4 & \inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_4 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_3 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [2]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [4]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [4]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .lut_mask = "c308";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X2_Y33_N9
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_3 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [4] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un1_line_counter_sig_combout [4]),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_3 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_3_ .lut_mask = "aaff";
+defparam \inst|vga_driver_unit|line_counter_sig_3_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_3_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_3_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_3_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X1_Y33_N7
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [5] = \inst|vga_driver_unit|line_counter_sig_4 $ (\inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout [3])
+// \inst|vga_driver_unit|un1_line_counter_sig_cout [5] = CARRY(\inst|vga_driver_unit|line_counter_sig_4 & \inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout [3])
+// \inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 = CARRY(\inst|vga_driver_unit|line_counter_sig_4 & \inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_4 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_3 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [3]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [5]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [5]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .lut_mask = "a608";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X1_Y33_N1
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_4 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [5] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .datac(\inst|vga_driver_unit|un1_line_counter_sig_combout [5]),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_4 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_4_ .lut_mask = "f3f3";
+defparam \inst|vga_driver_unit|line_counter_sig_4_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_4_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_4_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_4_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X2_Y33_N3
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [6] = \inst|vga_driver_unit|line_counter_sig_5 $ \inst|vga_driver_unit|un1_line_counter_sig_cout [4]
+// \inst|vga_driver_unit|un1_line_counter_sig_cout [6] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout [4] # !\inst|vga_driver_unit|line_counter_sig_5 # !\inst|vga_driver_unit|line_counter_sig_6 )
+// \inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 # !\inst|vga_driver_unit|line_counter_sig_5 # !\inst|vga_driver_unit|line_counter_sig_6 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_6 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_5 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [4]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [6]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [6]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .lut_mask = "3c7f";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X3_Y33_N2
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_5 = DFFEAS(\inst|vga_driver_unit|un10_line_counter_siglto8 & \inst|vga_driver_unit|un1_line_counter_sig_combout [6] & \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , GLOBAL(\inst1|altpll_component|_clk0 ),
+// VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .datac(\inst|vga_driver_unit|un1_line_counter_sig_combout [6]),
+ .datad(\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_5 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_5_ .lut_mask = "c000";
+defparam \inst|vga_driver_unit|line_counter_sig_5_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_5_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_5_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_5_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X2_Y33_N4
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_8_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [8] = \inst|vga_driver_unit|line_counter_sig_7 $ (!\inst|vga_driver_unit|un1_line_counter_sig_cout [6])
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_7 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [6]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [8]),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .lut_mask = "a5a5";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X2_Y33_N7
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_7_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_7 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [8] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un1_line_counter_sig_combout [8]),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_7 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_7_ .lut_mask = "aaff";
+defparam \inst|vga_driver_unit|line_counter_sig_7_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_7_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_7_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_7_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_7_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X1_Y33_N8
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_7_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [7] = \inst|vga_driver_unit|line_counter_sig_6 $ (\inst|vga_driver_unit|line_counter_sig_5 & \inst|vga_driver_unit|un1_line_counter_sig_cout [5])
+// \inst|vga_driver_unit|un1_line_counter_sig_cout [7] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout [5] # !\inst|vga_driver_unit|line_counter_sig_5 # !\inst|vga_driver_unit|line_counter_sig_6 )
+// \inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 # !\inst|vga_driver_unit|line_counter_sig_5 # !\inst|vga_driver_unit|line_counter_sig_6 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_6 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_5 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [5]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [7]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [7]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .lut_mask = "6a7f";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X1_Y33_N9
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_9_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [9] = \inst|vga_driver_unit|line_counter_sig_8 $ (\inst|vga_driver_unit|line_counter_sig_7 & !\inst|vga_driver_unit|un1_line_counter_sig_cout [7])
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_7 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|line_counter_sig_8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [7]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [9]),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .lut_mask = "f50a";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X1_Y33_N0
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_8_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_8 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [9] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .datad(\inst|vga_driver_unit|un1_line_counter_sig_combout [9]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_8 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_8_ .lut_mask = "ff0f";
+defparam \inst|vga_driver_unit|line_counter_sig_8_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_8_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_8_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_8_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_8_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X2_Y33_N8
+stratix_lcell \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_line_counter_siglt4_2 = !\inst|vga_driver_unit|line_counter_sig_3 # !\inst|vga_driver_unit|line_counter_sig_0 # !\inst|vga_driver_unit|line_counter_sig_4
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_4 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_0 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|line_counter_sig_3 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_line_counter_siglt4_2 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .lut_mask = "77ff";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X2_Y33_N5
+stratix_lcell \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_line_counter_siglto5 = !\inst|vga_driver_unit|line_counter_sig_5 & (\inst|vga_driver_unit|un10_line_counter_siglt4_2 # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_1 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_2 ),
+ .datac(\inst|vga_driver_unit|un10_line_counter_siglt4_2 ),
+ .datad(\inst|vga_driver_unit|line_counter_sig_5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_line_counter_siglto5 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .lut_mask = "00f7";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X2_Y33_N6
+stratix_lcell \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_line_counter_siglto8 = \inst|vga_driver_unit|un10_line_counter_siglto5 # !\inst|vga_driver_unit|line_counter_sig_6 # !\inst|vga_driver_unit|line_counter_sig_8 # !\inst|vga_driver_unit|line_counter_sig_7
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_7 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_8 ),
+ .datac(\inst|vga_driver_unit|line_counter_sig_6 ),
+ .datad(\inst|vga_driver_unit|un10_line_counter_siglto5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .lut_mask = "ff7f";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X1_Y33_N2
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_6 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [7] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .datad(\inst|vga_driver_unit|un1_line_counter_sig_combout [7]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_6 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_6_ .lut_mask = "ff0f";
+defparam \inst|vga_driver_unit|line_counter_sig_6_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_6_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_6_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_6_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X3_Y33_N5
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelt2 (
+// Equation(s):
+// \inst|vga_control_unit|un17_v_enablelt2 = \inst|vga_driver_unit|line_counter_sig_0 # \inst|vga_driver_unit|line_counter_sig_2 # \inst|vga_driver_unit|line_counter_sig_1
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_0 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_2 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|line_counter_sig_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un17_v_enablelt2 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelt2 .lut_mask = "ffee";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelt2 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelt2 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelt2 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelt2 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelt2 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X3_Y33_N8
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto5 (
+// Equation(s):
+// \inst|vga_control_unit|un17_v_enablelto5 = \inst|vga_driver_unit|line_counter_sig_4 # \inst|vga_driver_unit|line_counter_sig_5 # \inst|vga_control_unit|un17_v_enablelt2 & \inst|vga_driver_unit|line_counter_sig_3
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_4 ),
+ .datab(\inst|vga_control_unit|un17_v_enablelt2 ),
+ .datac(\inst|vga_driver_unit|line_counter_sig_3 ),
+ .datad(\inst|vga_driver_unit|line_counter_sig_5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un17_v_enablelto5 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto5 .lut_mask = "ffea";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto5 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto5 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto5 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto5 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto5 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X49_Y33_N1
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto7 (
+// Equation(s):
+// \inst|vga_control_unit|un17_v_enablelto7 = \inst|vga_driver_unit|line_counter_sig_6 & \inst|vga_driver_unit|line_counter_sig_7 & \inst|vga_control_unit|un17_v_enablelto5
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|line_counter_sig_6 ),
+ .datac(\inst|vga_driver_unit|line_counter_sig_7 ),
+ .datad(\inst|vga_control_unit|un17_v_enablelto5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un17_v_enablelto7 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto7 .lut_mask = "c000";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto7 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto7 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto7 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto7 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto7 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X23_Y42_N8
+stratix_lcell \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|hsync_state_5 & !\inst|vga_driver_unit|hsync_state_4
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_state_5 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_state_4 ),
+ .datad(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .lut_mask = "ff05";
+defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X23_Y43_N1
+stratix_lcell \inst|vga_driver_unit|v_enable_sig_Z (
+// Equation(s):
+// \inst|vga_driver_unit|v_enable_sig = DFFEAS(\inst|vga_driver_unit|hsync_state_3 # \inst|vga_driver_unit|hsync_state_1 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 , , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|hsync_state_3 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|hsync_state_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|v_enable_sig ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|v_enable_sig_Z .lut_mask = "ffcc";
+defparam \inst|vga_driver_unit|v_enable_sig_Z .operation_mode = "normal";
+defparam \inst|vga_driver_unit|v_enable_sig_Z .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|v_enable_sig_Z .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|v_enable_sig_Z .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|v_enable_sig_Z .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X49_Y33_N8
+stratix_lcell \inst|vga_control_unit|b_next_0_g0_3_cZ (
+// Equation(s):
+// \inst|vga_control_unit|b_next_0_g0_3 = \inst|vga_driver_unit|v_enable_sig & !\inst|vga_driver_unit|column_counter_sig_9 & !\inst|vga_driver_unit|line_counter_sig_8 & !\inst|vga_driver_unit|column_counter_sig_8
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|v_enable_sig ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_9 ),
+ .datac(\inst|vga_driver_unit|line_counter_sig_8 ),
+ .datad(\inst|vga_driver_unit|column_counter_sig_8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|b_next_0_g0_3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|b_next_0_g0_3_cZ .lut_mask = "0002";
+defparam \inst|vga_control_unit|b_next_0_g0_3_cZ .operation_mode = "normal";
+defparam \inst|vga_control_unit|b_next_0_g0_3_cZ .output_mode = "comb_only";
+defparam \inst|vga_control_unit|b_next_0_g0_3_cZ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|b_next_0_g0_3_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|b_next_0_g0_3_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y41_N1
+stratix_lcell \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|vsync_state_5 & !\inst|vga_driver_unit|vsync_state_4
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_state_5 ),
+ .datab(\inst|vga_driver_unit|vsync_state_4 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .lut_mask = "ff11";
+defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X49_Y33_N0
+stratix_lcell \inst|vga_driver_unit|h_enable_sig_Z (
+// Equation(s):
+// \inst|vga_driver_unit|h_enable_sig = DFFEAS(\inst|vga_driver_unit|vsync_state_3 # \inst|vga_driver_unit|vsync_state_1 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 , , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_state_3 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|vsync_state_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|h_enable_sig ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|h_enable_sig_Z .lut_mask = "ffaa";
+defparam \inst|vga_driver_unit|h_enable_sig_Z .operation_mode = "normal";
+defparam \inst|vga_driver_unit|h_enable_sig_Z .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|h_enable_sig_Z .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|h_enable_sig_Z .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|h_enable_sig_Z .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X49_Y33_N9
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 (
+// Equation(s):
+// \inst|vga_control_unit|un9_v_enablelto6 = \inst|vga_driver_unit|un10_column_counter_siglt6_1 # !\inst|vga_driver_unit|column_counter_sig_2 & !\inst|vga_driver_unit|column_counter_sig_3 & !\inst|vga_driver_unit|column_counter_sig_4
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_2 ),
+ .datab(\inst|vga_driver_unit|un10_column_counter_siglt6_1 ),
+ .datac(\inst|vga_driver_unit|column_counter_sig_3 ),
+ .datad(\inst|vga_driver_unit|column_counter_sig_4 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un9_v_enablelto6 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 .lut_mask = "cccd";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X49_Y33_N3
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto9 (
+// Equation(s):
+// \inst|vga_control_unit|un9_v_enablelto9 = !\inst|vga_driver_unit|column_counter_sig_8 & !\inst|vga_driver_unit|column_counter_sig_7 & !\inst|vga_driver_unit|column_counter_sig_9 & \inst|vga_control_unit|un9_v_enablelto6
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_8 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_7 ),
+ .datac(\inst|vga_driver_unit|column_counter_sig_9 ),
+ .datad(\inst|vga_control_unit|un9_v_enablelto6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un9_v_enablelto9 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto9 .lut_mask = "0100";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto9 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto9 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto9 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto9 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto9 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X50_Y46_N6
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_0_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_0 = DFFEAS(!\inst|vga_control_unit|toggle_counter_sig_0 , GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_0 ),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_0 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_0_ .lut_mask = "00ff";
+defparam \inst|vga_control_unit|toggle_counter_sig_0_ .operation_mode = "normal";
+defparam \inst|vga_control_unit|toggle_counter_sig_0_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_0_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|toggle_counter_sig_0_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y46_N0
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_1_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_1 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_0 $ \inst|vga_control_unit|toggle_counter_sig_1 , GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [1] = CARRY(\inst|vga_control_unit|toggle_counter_sig_0 & \inst|vga_control_unit|toggle_counter_sig_1 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17 = CARRY(\inst|vga_control_unit|toggle_counter_sig_0 & \inst|vga_control_unit|toggle_counter_sig_1 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_0 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_1 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_1 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [1]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_1_ .lut_mask = "6688";
+defparam \inst|vga_control_unit|toggle_counter_sig_1_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_1_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_1_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|toggle_counter_sig_1_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X52_Y46_N0
+stratix_lcell \inst|vga_control_unit|un2_toggle_counter_next_0_ (
+// Equation(s):
+// \inst|vga_control_unit|un2_toggle_counter_next_cout [0] = CARRY(\inst|vga_control_unit|toggle_counter_sig_1 & \inst|vga_control_unit|toggle_counter_sig_0 )
+// \inst|vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3 = CARRY(\inst|vga_control_unit|toggle_counter_sig_1 & \inst|vga_control_unit|toggle_counter_sig_0 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_1 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_0 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un2_toggle_counter_next_0_~COMBOUT ),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_control_unit|un2_toggle_counter_next_cout [0]),
+ .cout1(\inst|vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|un2_toggle_counter_next_0_ .lut_mask = "ff88";
+defparam \inst|vga_control_unit|un2_toggle_counter_next_0_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|un2_toggle_counter_next_0_ .output_mode = "none";
+defparam \inst|vga_control_unit|un2_toggle_counter_next_0_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|un2_toggle_counter_next_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|un2_toggle_counter_next_0_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y46_N1
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_2_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_2 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_2 $ \inst|vga_control_unit|un2_toggle_counter_next_cout [0], GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , ,
+// , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [2] = CARRY(!\inst|vga_control_unit|un2_toggle_counter_next_cout [0] # !\inst|vga_control_unit|toggle_counter_sig_2 # !\inst|vga_control_unit|toggle_counter_sig_3 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33 = CARRY(!\inst|vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3 # !\inst|vga_control_unit|toggle_counter_sig_2 # !\inst|vga_control_unit|toggle_counter_sig_3 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_3 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_2 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|un2_toggle_counter_next_cout [0]),
+ .cin1(\inst|vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_2 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [2]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .lut_mask = "3c7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y46_N1
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_3_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_3 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_3 $ (\inst|vga_control_unit|toggle_counter_sig_2 & \inst|vga_control_unit|toggle_counter_sig_cout [1]), GLOBAL(\inst1|altpll_component|_clk0 ),
+// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [3] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [1] # !\inst|vga_control_unit|toggle_counter_sig_3 # !\inst|vga_control_unit|toggle_counter_sig_2 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19 = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17 # !\inst|vga_control_unit|toggle_counter_sig_3 # !\inst|vga_control_unit|toggle_counter_sig_2 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_2 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_3 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [1]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_3 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [3]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .lut_mask = "6c7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X52_Y46_N2
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_4_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_4 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_4 $ (!\inst|vga_control_unit|toggle_counter_sig_cout [2]), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , ,
+// , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [4] = CARRY(\inst|vga_control_unit|toggle_counter_sig_4 & \inst|vga_control_unit|toggle_counter_sig_5 & !\inst|vga_control_unit|toggle_counter_sig_cout [2])
+// \inst|vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35 = CARRY(\inst|vga_control_unit|toggle_counter_sig_4 & \inst|vga_control_unit|toggle_counter_sig_5 & !\inst|vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_4 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_5 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [2]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_4 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [4]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .lut_mask = "a508";
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y46_N2
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_5_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_5 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_5 $ (\inst|vga_control_unit|toggle_counter_sig_4 & !\inst|vga_control_unit|toggle_counter_sig_cout [3]), GLOBAL(\inst1|altpll_component|_clk0 ),
+// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [5] = CARRY(\inst|vga_control_unit|toggle_counter_sig_5 & \inst|vga_control_unit|toggle_counter_sig_4 & !\inst|vga_control_unit|toggle_counter_sig_cout [3])
+// \inst|vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21 = CARRY(\inst|vga_control_unit|toggle_counter_sig_5 & \inst|vga_control_unit|toggle_counter_sig_4 & !\inst|vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_5 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_4 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [3]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_5 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [5]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .lut_mask = "a608";
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y46_N3
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_7_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_7 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_7 $ (\inst|vga_control_unit|toggle_counter_sig_6 & \inst|vga_control_unit|toggle_counter_sig_cout [5]), GLOBAL(\inst1|altpll_component|_clk0 ),
+// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [7] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [5] # !\inst|vga_control_unit|toggle_counter_sig_7 # !\inst|vga_control_unit|toggle_counter_sig_6 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23 = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21 # !\inst|vga_control_unit|toggle_counter_sig_7 # !\inst|vga_control_unit|toggle_counter_sig_6 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_6 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_7 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [5]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_7 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [7]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .lut_mask = "6c7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X52_Y46_N3
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_6_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_6 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_6 $ (\inst|vga_control_unit|toggle_counter_sig_cout [4]), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [6] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [4] # !\inst|vga_control_unit|toggle_counter_sig_7 # !\inst|vga_control_unit|toggle_counter_sig_6 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37 = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35 # !\inst|vga_control_unit|toggle_counter_sig_7 # !\inst|vga_control_unit|toggle_counter_sig_6 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_6 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_7 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [4]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_6 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [6]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .lut_mask = "5a7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y46_N4
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_9_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_9 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_9 $ (\inst|vga_control_unit|toggle_counter_sig_8 & !\inst|vga_control_unit|toggle_counter_sig_cout [7]), GLOBAL(\inst1|altpll_component|_clk0 ),
+// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [9] = CARRY(\inst|vga_control_unit|toggle_counter_sig_8 & \inst|vga_control_unit|toggle_counter_sig_9 & !\inst|vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_8 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_9 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [7]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_9 ),
+ .cout(\inst|vga_control_unit|toggle_counter_sig_cout [9]),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .lut_mask = "c608";
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X52_Y46_N4
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_8_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_8 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_8 $ (!\inst|vga_control_unit|toggle_counter_sig_cout [6]), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , ,
+// , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [8] = CARRY(\inst|vga_control_unit|toggle_counter_sig_8 & \inst|vga_control_unit|toggle_counter_sig_9 & !\inst|vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_8 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_9 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [6]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_8 ),
+ .cout(\inst|vga_control_unit|toggle_counter_sig_cout [8]),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .lut_mask = "a508";
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X50_Y46_N5
+stratix_lcell \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7_4 (
+// Equation(s):
+// \inst|vga_control_unit|un1_toggle_counter_siglto7_4 = !\inst|vga_control_unit|toggle_counter_sig_7 & !\inst|vga_control_unit|toggle_counter_sig_5 & !\inst|vga_control_unit|toggle_counter_sig_1 & !\inst|vga_control_unit|toggle_counter_sig_6
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_7 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_5 ),
+ .datac(\inst|vga_control_unit|toggle_counter_sig_1 ),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un1_toggle_counter_siglto7_4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7_4 .lut_mask = "0001";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7_4 .operation_mode = "normal";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7_4 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7_4 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7_4 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7_4 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X50_Y46_N9
+stratix_lcell \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7 (
+// Equation(s):
+// \inst|vga_control_unit|un1_toggle_counter_siglto7 = !\inst|vga_control_unit|toggle_counter_sig_3 & !\inst|vga_control_unit|toggle_counter_sig_4 & \inst|vga_control_unit|un1_toggle_counter_siglto7_4 & !\inst|vga_control_unit|toggle_counter_sig_2
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_3 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_4 ),
+ .datac(\inst|vga_control_unit|un1_toggle_counter_siglto7_4 ),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_2 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un1_toggle_counter_siglto7 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7 .lut_mask = "0010";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7 .operation_mode = "normal";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X51_Y46_N5
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_11_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_11 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_11 $ (\inst|vga_control_unit|toggle_counter_sig_10 & \inst|vga_control_unit|toggle_counter_sig_cout [9]), GLOBAL(\inst1|altpll_component|_clk0 ),
+// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [11] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [9] # !\inst|vga_control_unit|toggle_counter_sig_11 # !\inst|vga_control_unit|toggle_counter_sig_10 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25 = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [9] # !\inst|vga_control_unit|toggle_counter_sig_11 # !\inst|vga_control_unit|toggle_counter_sig_10 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_10 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_11 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [9]),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_11 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [11]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_11_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_11_ .lut_mask = "6c7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_11_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_11_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_11_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_11_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_11_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X52_Y46_N5
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_10_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_10 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_10 $ \inst|vga_control_unit|toggle_counter_sig_cout [8], GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [10] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [8] # !\inst|vga_control_unit|toggle_counter_sig_10 # !\inst|vga_control_unit|toggle_counter_sig_11 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39 = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [8] # !\inst|vga_control_unit|toggle_counter_sig_10 # !\inst|vga_control_unit|toggle_counter_sig_11 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_11 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_10 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [8]),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_10 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [10]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_10_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_10_ .lut_mask = "3c7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_10_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_10_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_10_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_10_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_10_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X50_Y46_N8
+stratix_lcell \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto10 (
+// Equation(s):
+// \inst|vga_control_unit|un1_toggle_counter_siglto10 = !\inst|vga_control_unit|toggle_counter_sig_9 & (\inst|vga_control_unit|un1_toggle_counter_siglto7 # !\inst|vga_control_unit|toggle_counter_sig_8 ) # !\inst|vga_control_unit|toggle_counter_sig_10
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_8 ),
+ .datab(\inst|vga_control_unit|un1_toggle_counter_siglto7 ),
+ .datac(\inst|vga_control_unit|toggle_counter_sig_9 ),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_10 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un1_toggle_counter_siglto10 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto10 .lut_mask = "0dff";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto10 .operation_mode = "normal";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto10 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto10 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto10 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto10 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y46_N6
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_12_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_12 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_12 $ !(!\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout [10]) #
+// (\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39 ), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [12] = CARRY(\inst|vga_control_unit|toggle_counter_sig_13 & \inst|vga_control_unit|toggle_counter_sig_12 & !\inst|vga_control_unit|toggle_counter_sig_cout [10])
+// \inst|vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41 = CARRY(\inst|vga_control_unit|toggle_counter_sig_13 & \inst|vga_control_unit|toggle_counter_sig_12 & !\inst|vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_13 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_12 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [8]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [10]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_12 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [12]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .lut_mask = "c308";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y46_N6
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_13_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_13 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_13 $ (\inst|vga_control_unit|toggle_counter_sig_12 & !(!\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout
+// [11]) # (\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25 )), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [13] = CARRY(\inst|vga_control_unit|toggle_counter_sig_13 & \inst|vga_control_unit|toggle_counter_sig_12 & !\inst|vga_control_unit|toggle_counter_sig_cout [11])
+// \inst|vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27 = CARRY(\inst|vga_control_unit|toggle_counter_sig_13 & \inst|vga_control_unit|toggle_counter_sig_12 & !\inst|vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_13 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_12 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [9]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [11]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_13 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [13]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .lut_mask = "a608";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y46_N7
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_15_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_15 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_15 $ (\inst|vga_control_unit|toggle_counter_sig_14 & (!\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout
+// [13]) # (\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27 )), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [15] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [13] # !\inst|vga_control_unit|toggle_counter_sig_15 # !\inst|vga_control_unit|toggle_counter_sig_14 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29 = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27 # !\inst|vga_control_unit|toggle_counter_sig_15 # !\inst|vga_control_unit|toggle_counter_sig_14 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_14 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_15 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [9]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [13]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_15 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [15]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .lut_mask = "6c7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X52_Y46_N7
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_14_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_14 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_14 $ ((!\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout [12]) #
+// (\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41 )), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [14] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [12] # !\inst|vga_control_unit|toggle_counter_sig_15 # !\inst|vga_control_unit|toggle_counter_sig_14 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43 = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41 # !\inst|vga_control_unit|toggle_counter_sig_15 # !\inst|vga_control_unit|toggle_counter_sig_14 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_14 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_15 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [8]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [12]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_14 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [14]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .lut_mask = "5a7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y46_N8
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_17_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_17 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_17 $ (\inst|vga_control_unit|toggle_counter_sig_16 & !(!\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout
+// [15]) # (\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29 )), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [17] = CARRY(\inst|vga_control_unit|toggle_counter_sig_17 & \inst|vga_control_unit|toggle_counter_sig_16 & !\inst|vga_control_unit|toggle_counter_sig_cout [15])
+// \inst|vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31 = CARRY(\inst|vga_control_unit|toggle_counter_sig_17 & \inst|vga_control_unit|toggle_counter_sig_16 & !\inst|vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_17 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_16 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [9]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [15]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_17 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [17]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .lut_mask = "a608";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X52_Y46_N8
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_16_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_16 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_16 $ (!(!\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout [14]) #
+// (\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43 )), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [16] = CARRY(\inst|vga_control_unit|toggle_counter_sig_16 & \inst|vga_control_unit|toggle_counter_sig_17 & !\inst|vga_control_unit|toggle_counter_sig_cout [14])
+// \inst|vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45 = CARRY(\inst|vga_control_unit|toggle_counter_sig_16 & \inst|vga_control_unit|toggle_counter_sig_17 & !\inst|vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_16 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_17 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [8]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [14]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_16 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [16]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .lut_mask = "a508";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X52_Y46_N9
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_18_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_18 = DFFEAS((!\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout [16]) # (\inst|vga_control_unit|toggle_counter_sig_cout [8] &
+// \inst|vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45 ) $ \inst|vga_control_unit|toggle_counter_sig_18 , GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1
+// , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_18 ),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [8]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [16]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_18 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .lut_mask = "0ff0";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .operation_mode = "normal";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y46_N9
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_19_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_19 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_19 $ ((!\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout [17]) #
+// (\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31 ) & \inst|vga_control_unit|toggle_counter_sig_18 ), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x
+// ), , , , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_19 ),
+ .datac(vcc),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_18 ),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [9]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [17]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_19 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .lut_mask = "3ccc";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .operation_mode = "normal";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X50_Y46_N1
+stratix_lcell \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_4 (
+// Equation(s):
+// \inst|vga_control_unit|un1_toggle_counter_siglto19_4 = !\inst|vga_control_unit|toggle_counter_sig_18 # !\inst|vga_control_unit|toggle_counter_sig_17 # !\inst|vga_control_unit|toggle_counter_sig_19 # !\inst|vga_control_unit|toggle_counter_sig_16
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_16 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_19 ),
+ .datac(\inst|vga_control_unit|toggle_counter_sig_17 ),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_18 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un1_toggle_counter_siglto19_4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_4 .lut_mask = "7fff";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_4 .operation_mode = "normal";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_4 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_4 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_4 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_4 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X50_Y46_N7
+stratix_lcell \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_5 (
+// Equation(s):
+// \inst|vga_control_unit|un1_toggle_counter_siglto19_5 = \inst|vga_control_unit|un1_toggle_counter_siglto19_4 # !\inst|vga_control_unit|toggle_counter_sig_14 # !\inst|vga_control_unit|toggle_counter_sig_15 # !\inst|vga_control_unit|toggle_counter_sig_13
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_13 ),
+ .datab(\inst|vga_control_unit|un1_toggle_counter_siglto19_4 ),
+ .datac(\inst|vga_control_unit|toggle_counter_sig_15 ),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_14 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un1_toggle_counter_siglto19_5 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_5 .lut_mask = "dfff";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_5 .operation_mode = "normal";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_5 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_5 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_5 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_5 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X50_Y46_N3
+stratix_lcell \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19 (
+// Equation(s):
+// \inst|vga_control_unit|un1_toggle_counter_siglto19 = \inst|vga_control_unit|un1_toggle_counter_siglto19_5 # \inst|vga_control_unit|un1_toggle_counter_siglto10 & !\inst|vga_control_unit|toggle_counter_sig_11 &
+// !\inst|vga_control_unit|toggle_counter_sig_12
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|un1_toggle_counter_siglto10 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_11 ),
+ .datac(\inst|vga_control_unit|un1_toggle_counter_siglto19_5 ),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_12 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un1_toggle_counter_siglto19 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19 .lut_mask = "f0f2";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19 .operation_mode = "normal";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X50_Y46_N4
+stratix_lcell \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_sig_0_0_0_g1 = \inst|vga_control_unit|un1_toggle_counter_siglto19
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_control_unit|un1_toggle_counter_siglto19 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ .lut_mask = "ff00";
+defparam \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ .operation_mode = "normal";
+defparam \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ .output_mode = "comb_only";
+defparam \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X50_Y46_N2
+stratix_lcell \inst|vga_control_unit|toggle_sig_Z (
+// Equation(s):
+// \inst|vga_control_unit|toggle_sig = DFFEAS(\inst|vga_control_unit|toggle_sig $ (!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_sig ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_sig ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_sig_Z .lut_mask = "aa55";
+defparam \inst|vga_control_unit|toggle_sig_Z .operation_mode = "normal";
+defparam \inst|vga_control_unit|toggle_sig_Z .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_sig_Z .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_sig_Z .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|toggle_sig_Z .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X49_Y33_N7
+stratix_lcell \inst|vga_control_unit|b_next_0_g0_5_cZ (
+// Equation(s):
+// \inst|vga_control_unit|b_next_0_g0_5 = \inst|vga_control_unit|b_next_0_g0_3 & \inst|vga_driver_unit|h_enable_sig & !\inst|vga_control_unit|un9_v_enablelto9 & \inst|vga_control_unit|toggle_sig
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|b_next_0_g0_3 ),
+ .datab(\inst|vga_driver_unit|h_enable_sig ),
+ .datac(\inst|vga_control_unit|un9_v_enablelto9 ),
+ .datad(\inst|vga_control_unit|toggle_sig ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|b_next_0_g0_5 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|b_next_0_g0_5_cZ .lut_mask = "0800";
+defparam \inst|vga_control_unit|b_next_0_g0_5_cZ .operation_mode = "normal";
+defparam \inst|vga_control_unit|b_next_0_g0_5_cZ .output_mode = "comb_only";
+defparam \inst|vga_control_unit|b_next_0_g0_5_cZ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|b_next_0_g0_5_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|b_next_0_g0_5_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X3_Y33_N6
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8_a (
+// Equation(s):
+// \inst|vga_control_unit|un13_v_enablelto8_a = !\inst|vga_driver_unit|line_counter_sig_4 & !\inst|vga_driver_unit|line_counter_sig_2 & !\inst|vga_driver_unit|line_counter_sig_3 # !\inst|vga_driver_unit|line_counter_sig_5
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_4 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_2 ),
+ .datac(\inst|vga_driver_unit|line_counter_sig_3 ),
+ .datad(\inst|vga_driver_unit|line_counter_sig_5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un13_v_enablelto8_a ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8_a .lut_mask = "01ff";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8_a .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8_a .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8_a .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8_a .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8_a .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X49_Y33_N5
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8 (
+// Equation(s):
+// \inst|vga_control_unit|un13_v_enablelto8 = !\inst|vga_driver_unit|line_counter_sig_8 & !\inst|vga_driver_unit|line_counter_sig_7 & (\inst|vga_control_unit|un13_v_enablelto8_a # !\inst|vga_driver_unit|line_counter_sig_6 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_8 ),
+ .datab(\inst|vga_control_unit|un13_v_enablelto8_a ),
+ .datac(\inst|vga_driver_unit|line_counter_sig_7 ),
+ .datad(\inst|vga_driver_unit|line_counter_sig_6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un13_v_enablelto8 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8 .lut_mask = "0405";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X49_Y33_N6
+stratix_lcell \inst|vga_control_unit|b_Z (
+// Equation(s):
+// \inst|vga_control_unit|b = DFFEAS(!\inst|vga_control_unit|un5_v_enablelto7 & !\inst|vga_control_unit|un17_v_enablelto7 & \inst|vga_control_unit|b_next_0_g0_5 & !\inst|vga_control_unit|un13_v_enablelto8 , GLOBAL(\inst1|altpll_component|_clk0 ),
+// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|un5_v_enablelto7 ),
+ .datab(\inst|vga_control_unit|un17_v_enablelto7 ),
+ .datac(\inst|vga_control_unit|b_next_0_g0_5 ),
+ .datad(\inst|vga_control_unit|un13_v_enablelto8 ),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|b ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|b_Z .lut_mask = "0010";
+defparam \inst|vga_control_unit|b_Z .operation_mode = "normal";
+defparam \inst|vga_control_unit|b_Z .output_mode = "reg_only";
+defparam \inst|vga_control_unit|b_Z .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|b_Z .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|b_Z .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at PIN_L7
+stratix_io \inst|d_hsync_out~I (
+ .datain(\inst|vga_driver_unit|h_sync ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_out~I .ddio_mode = "none";
+defparam \inst|d_hsync_out~I .input_async_reset = "none";
+defparam \inst|d_hsync_out~I .input_power_up = "low";
+defparam \inst|d_hsync_out~I .input_register_mode = "none";
+defparam \inst|d_hsync_out~I .input_sync_reset = "none";
+defparam \inst|d_hsync_out~I .oe_async_reset = "none";
+defparam \inst|d_hsync_out~I .oe_power_up = "low";
+defparam \inst|d_hsync_out~I .oe_register_mode = "none";
+defparam \inst|d_hsync_out~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_out~I .operation_mode = "output";
+defparam \inst|d_hsync_out~I .output_async_reset = "none";
+defparam \inst|d_hsync_out~I .output_power_up = "low";
+defparam \inst|d_hsync_out~I .output_register_mode = "none";
+defparam \inst|d_hsync_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L5
+stratix_io \inst|d_vsync_out~I (
+ .datain(\inst|vga_driver_unit|v_sync ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_out~I .ddio_mode = "none";
+defparam \inst|d_vsync_out~I .input_async_reset = "none";
+defparam \inst|d_vsync_out~I .input_power_up = "low";
+defparam \inst|d_vsync_out~I .input_register_mode = "none";
+defparam \inst|d_vsync_out~I .input_sync_reset = "none";
+defparam \inst|d_vsync_out~I .oe_async_reset = "none";
+defparam \inst|d_vsync_out~I .oe_power_up = "low";
+defparam \inst|d_vsync_out~I .oe_register_mode = "none";
+defparam \inst|d_vsync_out~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_out~I .operation_mode = "output";
+defparam \inst|d_vsync_out~I .output_async_reset = "none";
+defparam \inst|d_vsync_out~I .output_power_up = "low";
+defparam \inst|d_vsync_out~I .output_register_mode = "none";
+defparam \inst|d_vsync_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_Y23
+stratix_io \inst|d_set_column_counter_out~I (
+ .datain(\inst|vga_driver_unit|hsync_state_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_set_column_counter),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_set_column_counter_out~I .ddio_mode = "none";
+defparam \inst|d_set_column_counter_out~I .input_async_reset = "none";
+defparam \inst|d_set_column_counter_out~I .input_power_up = "low";
+defparam \inst|d_set_column_counter_out~I .input_register_mode = "none";
+defparam \inst|d_set_column_counter_out~I .input_sync_reset = "none";
+defparam \inst|d_set_column_counter_out~I .oe_async_reset = "none";
+defparam \inst|d_set_column_counter_out~I .oe_power_up = "low";
+defparam \inst|d_set_column_counter_out~I .oe_register_mode = "none";
+defparam \inst|d_set_column_counter_out~I .oe_sync_reset = "none";
+defparam \inst|d_set_column_counter_out~I .operation_mode = "output";
+defparam \inst|d_set_column_counter_out~I .output_async_reset = "none";
+defparam \inst|d_set_column_counter_out~I .output_power_up = "low";
+defparam \inst|d_set_column_counter_out~I .output_register_mode = "none";
+defparam \inst|d_set_column_counter_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F21
+stratix_io \inst|d_set_line_counter_out~I (
+ .datain(\inst|vga_driver_unit|vsync_state_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_set_line_counter),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_set_line_counter_out~I .ddio_mode = "none";
+defparam \inst|d_set_line_counter_out~I .input_async_reset = "none";
+defparam \inst|d_set_line_counter_out~I .input_power_up = "low";
+defparam \inst|d_set_line_counter_out~I .input_register_mode = "none";
+defparam \inst|d_set_line_counter_out~I .input_sync_reset = "none";
+defparam \inst|d_set_line_counter_out~I .oe_async_reset = "none";
+defparam \inst|d_set_line_counter_out~I .oe_power_up = "low";
+defparam \inst|d_set_line_counter_out~I .oe_register_mode = "none";
+defparam \inst|d_set_line_counter_out~I .oe_sync_reset = "none";
+defparam \inst|d_set_line_counter_out~I .operation_mode = "output";
+defparam \inst|d_set_line_counter_out~I .output_async_reset = "none";
+defparam \inst|d_set_line_counter_out~I .output_power_up = "low";
+defparam \inst|d_set_line_counter_out~I .output_register_mode = "none";
+defparam \inst|d_set_line_counter_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F26
+stratix_io \inst|d_set_hsync_counter_out~I (
+ .datain(\inst|vga_driver_unit|d_set_hsync_counter ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_set_hsync_counter),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_set_hsync_counter_out~I .ddio_mode = "none";
+defparam \inst|d_set_hsync_counter_out~I .input_async_reset = "none";
+defparam \inst|d_set_hsync_counter_out~I .input_power_up = "low";
+defparam \inst|d_set_hsync_counter_out~I .input_register_mode = "none";
+defparam \inst|d_set_hsync_counter_out~I .input_sync_reset = "none";
+defparam \inst|d_set_hsync_counter_out~I .oe_async_reset = "none";
+defparam \inst|d_set_hsync_counter_out~I .oe_power_up = "low";
+defparam \inst|d_set_hsync_counter_out~I .oe_register_mode = "none";
+defparam \inst|d_set_hsync_counter_out~I .oe_sync_reset = "none";
+defparam \inst|d_set_hsync_counter_out~I .operation_mode = "output";
+defparam \inst|d_set_hsync_counter_out~I .output_async_reset = "none";
+defparam \inst|d_set_hsync_counter_out~I .output_power_up = "low";
+defparam \inst|d_set_hsync_counter_out~I .output_register_mode = "none";
+defparam \inst|d_set_hsync_counter_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F24
+stratix_io \inst|d_set_vsync_counter_out~I (
+ .datain(\inst|vga_driver_unit|d_set_vsync_counter ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_set_vsync_counter),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_set_vsync_counter_out~I .ddio_mode = "none";
+defparam \inst|d_set_vsync_counter_out~I .input_async_reset = "none";
+defparam \inst|d_set_vsync_counter_out~I .input_power_up = "low";
+defparam \inst|d_set_vsync_counter_out~I .input_register_mode = "none";
+defparam \inst|d_set_vsync_counter_out~I .input_sync_reset = "none";
+defparam \inst|d_set_vsync_counter_out~I .oe_async_reset = "none";
+defparam \inst|d_set_vsync_counter_out~I .oe_power_up = "low";
+defparam \inst|d_set_vsync_counter_out~I .oe_register_mode = "none";
+defparam \inst|d_set_vsync_counter_out~I .oe_sync_reset = "none";
+defparam \inst|d_set_vsync_counter_out~I .operation_mode = "output";
+defparam \inst|d_set_vsync_counter_out~I .output_async_reset = "none";
+defparam \inst|d_set_vsync_counter_out~I .output_power_up = "low";
+defparam \inst|d_set_vsync_counter_out~I .output_register_mode = "none";
+defparam \inst|d_set_vsync_counter_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L3
+stratix_io \inst|d_r_out~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_r),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_r_out~I .ddio_mode = "none";
+defparam \inst|d_r_out~I .input_async_reset = "none";
+defparam \inst|d_r_out~I .input_power_up = "low";
+defparam \inst|d_r_out~I .input_register_mode = "none";
+defparam \inst|d_r_out~I .input_sync_reset = "none";
+defparam \inst|d_r_out~I .oe_async_reset = "none";
+defparam \inst|d_r_out~I .oe_power_up = "low";
+defparam \inst|d_r_out~I .oe_register_mode = "none";
+defparam \inst|d_r_out~I .oe_sync_reset = "none";
+defparam \inst|d_r_out~I .operation_mode = "output";
+defparam \inst|d_r_out~I .output_async_reset = "none";
+defparam \inst|d_r_out~I .output_power_up = "low";
+defparam \inst|d_r_out~I .output_register_mode = "none";
+defparam \inst|d_r_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K24
+stratix_io \inst|d_g_out~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_g),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_g_out~I .ddio_mode = "none";
+defparam \inst|d_g_out~I .input_async_reset = "none";
+defparam \inst|d_g_out~I .input_power_up = "low";
+defparam \inst|d_g_out~I .input_register_mode = "none";
+defparam \inst|d_g_out~I .input_sync_reset = "none";
+defparam \inst|d_g_out~I .oe_async_reset = "none";
+defparam \inst|d_g_out~I .oe_power_up = "low";
+defparam \inst|d_g_out~I .oe_register_mode = "none";
+defparam \inst|d_g_out~I .oe_sync_reset = "none";
+defparam \inst|d_g_out~I .operation_mode = "output";
+defparam \inst|d_g_out~I .output_async_reset = "none";
+defparam \inst|d_g_out~I .output_power_up = "low";
+defparam \inst|d_g_out~I .output_register_mode = "none";
+defparam \inst|d_g_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K20
+stratix_io \inst|d_b_out~I (
+ .datain(\inst|vga_control_unit|b ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_b),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_b_out~I .ddio_mode = "none";
+defparam \inst|d_b_out~I .input_async_reset = "none";
+defparam \inst|d_b_out~I .input_power_up = "low";
+defparam \inst|d_b_out~I .input_register_mode = "none";
+defparam \inst|d_b_out~I .input_sync_reset = "none";
+defparam \inst|d_b_out~I .oe_async_reset = "none";
+defparam \inst|d_b_out~I .oe_power_up = "low";
+defparam \inst|d_b_out~I .oe_register_mode = "none";
+defparam \inst|d_b_out~I .oe_sync_reset = "none";
+defparam \inst|d_b_out~I .operation_mode = "output";
+defparam \inst|d_b_out~I .output_async_reset = "none";
+defparam \inst|d_b_out~I .output_power_up = "low";
+defparam \inst|d_b_out~I .output_register_mode = "none";
+defparam \inst|d_b_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_J21
+stratix_io \inst|d_h_enable_out~I (
+ .datain(\inst|vga_driver_unit|h_enable_sig ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_h_enable),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_h_enable_out~I .ddio_mode = "none";
+defparam \inst|d_h_enable_out~I .input_async_reset = "none";
+defparam \inst|d_h_enable_out~I .input_power_up = "low";
+defparam \inst|d_h_enable_out~I .input_register_mode = "none";
+defparam \inst|d_h_enable_out~I .input_sync_reset = "none";
+defparam \inst|d_h_enable_out~I .oe_async_reset = "none";
+defparam \inst|d_h_enable_out~I .oe_power_up = "low";
+defparam \inst|d_h_enable_out~I .oe_register_mode = "none";
+defparam \inst|d_h_enable_out~I .oe_sync_reset = "none";
+defparam \inst|d_h_enable_out~I .operation_mode = "output";
+defparam \inst|d_h_enable_out~I .output_async_reset = "none";
+defparam \inst|d_h_enable_out~I .output_power_up = "low";
+defparam \inst|d_h_enable_out~I .output_register_mode = "none";
+defparam \inst|d_h_enable_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H18
+stratix_io \inst|d_v_enable_out~I (
+ .datain(\inst|vga_driver_unit|v_enable_sig ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_v_enable),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_v_enable_out~I .ddio_mode = "none";
+defparam \inst|d_v_enable_out~I .input_async_reset = "none";
+defparam \inst|d_v_enable_out~I .input_power_up = "low";
+defparam \inst|d_v_enable_out~I .input_register_mode = "none";
+defparam \inst|d_v_enable_out~I .input_sync_reset = "none";
+defparam \inst|d_v_enable_out~I .oe_async_reset = "none";
+defparam \inst|d_v_enable_out~I .oe_power_up = "low";
+defparam \inst|d_v_enable_out~I .oe_register_mode = "none";
+defparam \inst|d_v_enable_out~I .oe_sync_reset = "none";
+defparam \inst|d_v_enable_out~I .operation_mode = "output";
+defparam \inst|d_v_enable_out~I .output_async_reset = "none";
+defparam \inst|d_v_enable_out~I .output_power_up = "low";
+defparam \inst|d_v_enable_out~I .output_register_mode = "none";
+defparam \inst|d_v_enable_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K3
+stratix_io \inst|d_state_clk_out~I (
+ .datain(\inst1|altpll_component|_clk0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_state_clk),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_state_clk_out~I .ddio_mode = "none";
+defparam \inst|d_state_clk_out~I .input_async_reset = "none";
+defparam \inst|d_state_clk_out~I .input_power_up = "low";
+defparam \inst|d_state_clk_out~I .input_register_mode = "none";
+defparam \inst|d_state_clk_out~I .input_sync_reset = "none";
+defparam \inst|d_state_clk_out~I .oe_async_reset = "none";
+defparam \inst|d_state_clk_out~I .oe_power_up = "low";
+defparam \inst|d_state_clk_out~I .oe_register_mode = "none";
+defparam \inst|d_state_clk_out~I .oe_sync_reset = "none";
+defparam \inst|d_state_clk_out~I .operation_mode = "output";
+defparam \inst|d_state_clk_out~I .output_async_reset = "none";
+defparam \inst|d_state_clk_out~I .output_power_up = "low";
+defparam \inst|d_state_clk_out~I .output_register_mode = "none";
+defparam \inst|d_state_clk_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H3
+stratix_io \inst|d_toggle_out~I (
+ .datain(\inst|vga_control_unit|toggle_sig ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_out~I .ddio_mode = "none";
+defparam \inst|d_toggle_out~I .input_async_reset = "none";
+defparam \inst|d_toggle_out~I .input_power_up = "low";
+defparam \inst|d_toggle_out~I .input_register_mode = "none";
+defparam \inst|d_toggle_out~I .input_sync_reset = "none";
+defparam \inst|d_toggle_out~I .oe_async_reset = "none";
+defparam \inst|d_toggle_out~I .oe_power_up = "low";
+defparam \inst|d_toggle_out~I .oe_register_mode = "none";
+defparam \inst|d_toggle_out~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_out~I .operation_mode = "output";
+defparam \inst|d_toggle_out~I .output_async_reset = "none";
+defparam \inst|d_toggle_out~I .output_power_up = "low";
+defparam \inst|d_toggle_out~I .output_register_mode = "none";
+defparam \inst|d_toggle_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_E22
+stratix_io \inst|r0_pin_out~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(r0_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|r0_pin_out~I .ddio_mode = "none";
+defparam \inst|r0_pin_out~I .input_async_reset = "none";
+defparam \inst|r0_pin_out~I .input_power_up = "low";
+defparam \inst|r0_pin_out~I .input_register_mode = "none";
+defparam \inst|r0_pin_out~I .input_sync_reset = "none";
+defparam \inst|r0_pin_out~I .oe_async_reset = "none";
+defparam \inst|r0_pin_out~I .oe_power_up = "low";
+defparam \inst|r0_pin_out~I .oe_register_mode = "none";
+defparam \inst|r0_pin_out~I .oe_sync_reset = "none";
+defparam \inst|r0_pin_out~I .operation_mode = "output";
+defparam \inst|r0_pin_out~I .output_async_reset = "none";
+defparam \inst|r0_pin_out~I .output_power_up = "low";
+defparam \inst|r0_pin_out~I .output_register_mode = "none";
+defparam \inst|r0_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_T4
+stratix_io \inst|r1_pin_out~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(r1_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|r1_pin_out~I .ddio_mode = "none";
+defparam \inst|r1_pin_out~I .input_async_reset = "none";
+defparam \inst|r1_pin_out~I .input_power_up = "low";
+defparam \inst|r1_pin_out~I .input_register_mode = "none";
+defparam \inst|r1_pin_out~I .input_sync_reset = "none";
+defparam \inst|r1_pin_out~I .oe_async_reset = "none";
+defparam \inst|r1_pin_out~I .oe_power_up = "low";
+defparam \inst|r1_pin_out~I .oe_register_mode = "none";
+defparam \inst|r1_pin_out~I .oe_sync_reset = "none";
+defparam \inst|r1_pin_out~I .operation_mode = "output";
+defparam \inst|r1_pin_out~I .output_async_reset = "none";
+defparam \inst|r1_pin_out~I .output_power_up = "low";
+defparam \inst|r1_pin_out~I .output_register_mode = "none";
+defparam \inst|r1_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_T7
+stratix_io \inst|r2_pin_out~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(r2_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|r2_pin_out~I .ddio_mode = "none";
+defparam \inst|r2_pin_out~I .input_async_reset = "none";
+defparam \inst|r2_pin_out~I .input_power_up = "low";
+defparam \inst|r2_pin_out~I .input_register_mode = "none";
+defparam \inst|r2_pin_out~I .input_sync_reset = "none";
+defparam \inst|r2_pin_out~I .oe_async_reset = "none";
+defparam \inst|r2_pin_out~I .oe_power_up = "low";
+defparam \inst|r2_pin_out~I .oe_register_mode = "none";
+defparam \inst|r2_pin_out~I .oe_sync_reset = "none";
+defparam \inst|r2_pin_out~I .operation_mode = "output";
+defparam \inst|r2_pin_out~I .output_async_reset = "none";
+defparam \inst|r2_pin_out~I .output_power_up = "low";
+defparam \inst|r2_pin_out~I .output_register_mode = "none";
+defparam \inst|r2_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_E23
+stratix_io \inst|g0_pin_out~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(g0_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|g0_pin_out~I .ddio_mode = "none";
+defparam \inst|g0_pin_out~I .input_async_reset = "none";
+defparam \inst|g0_pin_out~I .input_power_up = "low";
+defparam \inst|g0_pin_out~I .input_register_mode = "none";
+defparam \inst|g0_pin_out~I .input_sync_reset = "none";
+defparam \inst|g0_pin_out~I .oe_async_reset = "none";
+defparam \inst|g0_pin_out~I .oe_power_up = "low";
+defparam \inst|g0_pin_out~I .oe_register_mode = "none";
+defparam \inst|g0_pin_out~I .oe_sync_reset = "none";
+defparam \inst|g0_pin_out~I .operation_mode = "output";
+defparam \inst|g0_pin_out~I .output_async_reset = "none";
+defparam \inst|g0_pin_out~I .output_power_up = "low";
+defparam \inst|g0_pin_out~I .output_register_mode = "none";
+defparam \inst|g0_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_T5
+stratix_io \inst|g1_pin_out~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(g1_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|g1_pin_out~I .ddio_mode = "none";
+defparam \inst|g1_pin_out~I .input_async_reset = "none";
+defparam \inst|g1_pin_out~I .input_power_up = "low";
+defparam \inst|g1_pin_out~I .input_register_mode = "none";
+defparam \inst|g1_pin_out~I .input_sync_reset = "none";
+defparam \inst|g1_pin_out~I .oe_async_reset = "none";
+defparam \inst|g1_pin_out~I .oe_power_up = "low";
+defparam \inst|g1_pin_out~I .oe_register_mode = "none";
+defparam \inst|g1_pin_out~I .oe_sync_reset = "none";
+defparam \inst|g1_pin_out~I .operation_mode = "output";
+defparam \inst|g1_pin_out~I .output_async_reset = "none";
+defparam \inst|g1_pin_out~I .output_power_up = "low";
+defparam \inst|g1_pin_out~I .output_register_mode = "none";
+defparam \inst|g1_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_T24
+stratix_io \inst|g2_pin_out~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(g2_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|g2_pin_out~I .ddio_mode = "none";
+defparam \inst|g2_pin_out~I .input_async_reset = "none";
+defparam \inst|g2_pin_out~I .input_power_up = "low";
+defparam \inst|g2_pin_out~I .input_register_mode = "none";
+defparam \inst|g2_pin_out~I .input_sync_reset = "none";
+defparam \inst|g2_pin_out~I .oe_async_reset = "none";
+defparam \inst|g2_pin_out~I .oe_power_up = "low";
+defparam \inst|g2_pin_out~I .oe_register_mode = "none";
+defparam \inst|g2_pin_out~I .oe_sync_reset = "none";
+defparam \inst|g2_pin_out~I .operation_mode = "output";
+defparam \inst|g2_pin_out~I .output_async_reset = "none";
+defparam \inst|g2_pin_out~I .output_power_up = "low";
+defparam \inst|g2_pin_out~I .output_register_mode = "none";
+defparam \inst|g2_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_E24
+stratix_io \inst|b0_pin_out~I (
+ .datain(\inst|vga_control_unit|b ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(b0_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|b0_pin_out~I .ddio_mode = "none";
+defparam \inst|b0_pin_out~I .input_async_reset = "none";
+defparam \inst|b0_pin_out~I .input_power_up = "low";
+defparam \inst|b0_pin_out~I .input_register_mode = "none";
+defparam \inst|b0_pin_out~I .input_sync_reset = "none";
+defparam \inst|b0_pin_out~I .oe_async_reset = "none";
+defparam \inst|b0_pin_out~I .oe_power_up = "low";
+defparam \inst|b0_pin_out~I .oe_register_mode = "none";
+defparam \inst|b0_pin_out~I .oe_sync_reset = "none";
+defparam \inst|b0_pin_out~I .operation_mode = "output";
+defparam \inst|b0_pin_out~I .output_async_reset = "none";
+defparam \inst|b0_pin_out~I .output_power_up = "low";
+defparam \inst|b0_pin_out~I .output_register_mode = "none";
+defparam \inst|b0_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_T6
+stratix_io \inst|b1_pin_out~I (
+ .datain(\inst|vga_control_unit|b ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(b1_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|b1_pin_out~I .ddio_mode = "none";
+defparam \inst|b1_pin_out~I .input_async_reset = "none";
+defparam \inst|b1_pin_out~I .input_power_up = "low";
+defparam \inst|b1_pin_out~I .input_register_mode = "none";
+defparam \inst|b1_pin_out~I .input_sync_reset = "none";
+defparam \inst|b1_pin_out~I .oe_async_reset = "none";
+defparam \inst|b1_pin_out~I .oe_power_up = "low";
+defparam \inst|b1_pin_out~I .oe_register_mode = "none";
+defparam \inst|b1_pin_out~I .oe_sync_reset = "none";
+defparam \inst|b1_pin_out~I .operation_mode = "output";
+defparam \inst|b1_pin_out~I .output_async_reset = "none";
+defparam \inst|b1_pin_out~I .output_power_up = "low";
+defparam \inst|b1_pin_out~I .output_register_mode = "none";
+defparam \inst|b1_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F1
+stratix_io \inst|hsync_pin_out~I (
+ .datain(\inst|vga_driver_unit|h_sync ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(hsync_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|hsync_pin_out~I .ddio_mode = "none";
+defparam \inst|hsync_pin_out~I .input_async_reset = "none";
+defparam \inst|hsync_pin_out~I .input_power_up = "low";
+defparam \inst|hsync_pin_out~I .input_register_mode = "none";
+defparam \inst|hsync_pin_out~I .input_sync_reset = "none";
+defparam \inst|hsync_pin_out~I .oe_async_reset = "none";
+defparam \inst|hsync_pin_out~I .oe_power_up = "low";
+defparam \inst|hsync_pin_out~I .oe_register_mode = "none";
+defparam \inst|hsync_pin_out~I .oe_sync_reset = "none";
+defparam \inst|hsync_pin_out~I .operation_mode = "output";
+defparam \inst|hsync_pin_out~I .output_async_reset = "none";
+defparam \inst|hsync_pin_out~I .output_power_up = "low";
+defparam \inst|hsync_pin_out~I .output_register_mode = "none";
+defparam \inst|hsync_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F2
+stratix_io \inst|vsync_pin_out~I (
+ .datain(\inst|vga_driver_unit|v_sync ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(vsync_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|vsync_pin_out~I .ddio_mode = "none";
+defparam \inst|vsync_pin_out~I .input_async_reset = "none";
+defparam \inst|vsync_pin_out~I .input_power_up = "low";
+defparam \inst|vsync_pin_out~I .input_register_mode = "none";
+defparam \inst|vsync_pin_out~I .input_sync_reset = "none";
+defparam \inst|vsync_pin_out~I .oe_async_reset = "none";
+defparam \inst|vsync_pin_out~I .oe_power_up = "low";
+defparam \inst|vsync_pin_out~I .oe_register_mode = "none";
+defparam \inst|vsync_pin_out~I .oe_sync_reset = "none";
+defparam \inst|vsync_pin_out~I .operation_mode = "output";
+defparam \inst|vsync_pin_out~I .output_async_reset = "none";
+defparam \inst|vsync_pin_out~I .output_power_up = "low";
+defparam \inst|vsync_pin_out~I .output_register_mode = "none";
+defparam \inst|vsync_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K5
+stratix_io \inst|d_column_counter_out_9_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_9 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[9]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_9_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_9_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_9_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_9_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_9_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_9_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_9_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_9_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_9_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_9_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_9_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_9_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_9_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_9_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K19
+stratix_io \inst|d_column_counter_out_8_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_8 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[8]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_8_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_8_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_8_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_8_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_8_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_8_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_8_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_8_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_8_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_8_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_8_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_8_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_8_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_8_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K23
+stratix_io \inst|d_column_counter_out_7_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_7 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[7]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_7_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_7_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_7_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_7_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_7_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_7_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_7_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_7_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_7_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_7_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_7_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_7_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_7_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_7_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L2
+stratix_io \inst|d_column_counter_out_6_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_6 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_6_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_6_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_6_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_6_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_6_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_6_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_6_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_6_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_6_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_6_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_6_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_6_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_6_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L4
+stratix_io \inst|d_column_counter_out_5_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_5 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_5_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_5_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_5_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_5_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_5_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_5_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_5_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_5_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_5_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_5_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_5_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_5_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_5_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L6
+stratix_io \inst|d_column_counter_out_4_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_4 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_4_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_4_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_4_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_4_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_4_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_4_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_4_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_4_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_4_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_4_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_4_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_4_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_4_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L20
+stratix_io \inst|d_column_counter_out_3_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_3 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_3_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_3_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_3_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_3_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_3_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_3_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_3_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_3_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_3_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_3_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_3_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_3_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_3_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L21
+stratix_io \inst|d_column_counter_out_2_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_2 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_2_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_2_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_2_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_2_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_2_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_2_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_2_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_2_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_2_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_2_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_2_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_2_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_2_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L22
+stratix_io \inst|d_column_counter_out_1_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_1_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_1_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_1_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_1_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_1_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_1_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_1_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_1_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_1_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_1_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_1_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_1_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_1_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L23
+stratix_io \inst|d_column_counter_out_0_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_0_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_0_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_0_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_0_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_0_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_0_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_0_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_0_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_0_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_0_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_0_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_0_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_0_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G18
+stratix_io \inst|d_hsync_counter_out_9_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_9 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[9]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_9_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_9_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_9_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_9_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_9_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_9_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_9_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_9_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_9_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_9_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_9_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_9_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_9_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_9_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G22
+stratix_io \inst|d_hsync_counter_out_8_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_8 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[8]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_8_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_8_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_8_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_8_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_8_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_8_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_8_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_8_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_8_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_8_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_8_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_8_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_8_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_8_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G25
+stratix_io \inst|d_hsync_counter_out_7_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_7 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[7]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_7_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_7_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_7_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_7_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_7_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_7_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_7_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_7_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_7_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_7_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_7_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_7_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_7_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_7_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_C10
+stratix_io \inst|d_hsync_counter_out_6_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_6 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_6_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_6_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_6_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_6_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_6_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_6_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_6_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_6_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_6_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_6_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_6_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_6_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_6_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_A9
+stratix_io \inst|d_hsync_counter_out_5_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_5 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_5_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_5_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_5_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_5_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_5_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_5_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_5_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_5_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_5_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_5_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_5_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_5_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_5_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H1
+stratix_io \inst|d_hsync_counter_out_4_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_4 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_4_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_4_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_4_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_4_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_4_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_4_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_4_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_4_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_4_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_4_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_4_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_4_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_4_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_B10
+stratix_io \inst|d_hsync_counter_out_3_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_3 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_3_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_3_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_3_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_3_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_3_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_3_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_3_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_3_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_3_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_3_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_3_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_3_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_3_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_D10
+stratix_io \inst|d_hsync_counter_out_2_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_2 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_2_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_2_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_2_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_2_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_2_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_2_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_2_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_2_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_2_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_2_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_2_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_2_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_2_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_AC10
+stratix_io \inst|d_hsync_counter_out_1_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_1_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_1_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_1_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_1_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_1_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_1_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_1_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_1_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_1_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_1_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_1_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_1_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_1_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H4
+stratix_io \inst|d_hsync_counter_out_0_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_0_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_0_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_0_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_0_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_0_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_0_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_0_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_0_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_0_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_0_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_0_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_0_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_0_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_Y5
+stratix_io \inst|d_hsync_state_out_0_~I (
+ .datain(\inst|vga_driver_unit|hsync_state_0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_state[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_state_out_0_~I .ddio_mode = "none";
+defparam \inst|d_hsync_state_out_0_~I .input_async_reset = "none";
+defparam \inst|d_hsync_state_out_0_~I .input_power_up = "low";
+defparam \inst|d_hsync_state_out_0_~I .input_register_mode = "none";
+defparam \inst|d_hsync_state_out_0_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_state_out_0_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_state_out_0_~I .oe_power_up = "low";
+defparam \inst|d_hsync_state_out_0_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_state_out_0_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_state_out_0_~I .operation_mode = "output";
+defparam \inst|d_hsync_state_out_0_~I .output_async_reset = "none";
+defparam \inst|d_hsync_state_out_0_~I .output_power_up = "low";
+defparam \inst|d_hsync_state_out_0_~I .output_register_mode = "none";
+defparam \inst|d_hsync_state_out_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F19
+stratix_io \inst|d_hsync_state_out_1_~I (
+ .datain(\inst|vga_driver_unit|hsync_state_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_state[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_state_out_1_~I .ddio_mode = "none";
+defparam \inst|d_hsync_state_out_1_~I .input_async_reset = "none";
+defparam \inst|d_hsync_state_out_1_~I .input_power_up = "low";
+defparam \inst|d_hsync_state_out_1_~I .input_register_mode = "none";
+defparam \inst|d_hsync_state_out_1_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_state_out_1_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_state_out_1_~I .oe_power_up = "low";
+defparam \inst|d_hsync_state_out_1_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_state_out_1_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_state_out_1_~I .operation_mode = "output";
+defparam \inst|d_hsync_state_out_1_~I .output_async_reset = "none";
+defparam \inst|d_hsync_state_out_1_~I .output_power_up = "low";
+defparam \inst|d_hsync_state_out_1_~I .output_register_mode = "none";
+defparam \inst|d_hsync_state_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F17
+stratix_io \inst|d_hsync_state_out_2_~I (
+ .datain(\inst|vga_driver_unit|hsync_state_2 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_state[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_state_out_2_~I .ddio_mode = "none";
+defparam \inst|d_hsync_state_out_2_~I .input_async_reset = "none";
+defparam \inst|d_hsync_state_out_2_~I .input_power_up = "low";
+defparam \inst|d_hsync_state_out_2_~I .input_register_mode = "none";
+defparam \inst|d_hsync_state_out_2_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_state_out_2_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_state_out_2_~I .oe_power_up = "low";
+defparam \inst|d_hsync_state_out_2_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_state_out_2_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_state_out_2_~I .operation_mode = "output";
+defparam \inst|d_hsync_state_out_2_~I .output_async_reset = "none";
+defparam \inst|d_hsync_state_out_2_~I .output_power_up = "low";
+defparam \inst|d_hsync_state_out_2_~I .output_register_mode = "none";
+defparam \inst|d_hsync_state_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_Y2
+stratix_io \inst|d_hsync_state_out_3_~I (
+ .datain(\inst|vga_driver_unit|hsync_state_3 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_state[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_state_out_3_~I .ddio_mode = "none";
+defparam \inst|d_hsync_state_out_3_~I .input_async_reset = "none";
+defparam \inst|d_hsync_state_out_3_~I .input_power_up = "low";
+defparam \inst|d_hsync_state_out_3_~I .input_register_mode = "none";
+defparam \inst|d_hsync_state_out_3_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_state_out_3_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_state_out_3_~I .oe_power_up = "low";
+defparam \inst|d_hsync_state_out_3_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_state_out_3_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_state_out_3_~I .operation_mode = "output";
+defparam \inst|d_hsync_state_out_3_~I .output_async_reset = "none";
+defparam \inst|d_hsync_state_out_3_~I .output_power_up = "low";
+defparam \inst|d_hsync_state_out_3_~I .output_register_mode = "none";
+defparam \inst|d_hsync_state_out_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F10
+stratix_io \inst|d_hsync_state_out_4_~I (
+ .datain(\inst|vga_driver_unit|hsync_state_4 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_state[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_state_out_4_~I .ddio_mode = "none";
+defparam \inst|d_hsync_state_out_4_~I .input_async_reset = "none";
+defparam \inst|d_hsync_state_out_4_~I .input_power_up = "low";
+defparam \inst|d_hsync_state_out_4_~I .input_register_mode = "none";
+defparam \inst|d_hsync_state_out_4_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_state_out_4_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_state_out_4_~I .oe_power_up = "low";
+defparam \inst|d_hsync_state_out_4_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_state_out_4_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_state_out_4_~I .operation_mode = "output";
+defparam \inst|d_hsync_state_out_4_~I .output_async_reset = "none";
+defparam \inst|d_hsync_state_out_4_~I .output_power_up = "low";
+defparam \inst|d_hsync_state_out_4_~I .output_register_mode = "none";
+defparam \inst|d_hsync_state_out_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F9
+stratix_io \inst|d_hsync_state_out_5_~I (
+ .datain(\inst|vga_driver_unit|hsync_state_5 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_state[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_state_out_5_~I .ddio_mode = "none";
+defparam \inst|d_hsync_state_out_5_~I .input_async_reset = "none";
+defparam \inst|d_hsync_state_out_5_~I .input_power_up = "low";
+defparam \inst|d_hsync_state_out_5_~I .input_register_mode = "none";
+defparam \inst|d_hsync_state_out_5_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_state_out_5_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_state_out_5_~I .oe_power_up = "low";
+defparam \inst|d_hsync_state_out_5_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_state_out_5_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_state_out_5_~I .operation_mode = "output";
+defparam \inst|d_hsync_state_out_5_~I .output_async_reset = "none";
+defparam \inst|d_hsync_state_out_5_~I .output_power_up = "low";
+defparam \inst|d_hsync_state_out_5_~I .output_register_mode = "none";
+defparam \inst|d_hsync_state_out_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F6
+stratix_io \inst|d_hsync_state_out_6_~I (
+ .datain(\inst|vga_driver_unit|hsync_state_6 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_state[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_state_out_6_~I .ddio_mode = "none";
+defparam \inst|d_hsync_state_out_6_~I .input_async_reset = "none";
+defparam \inst|d_hsync_state_out_6_~I .input_power_up = "low";
+defparam \inst|d_hsync_state_out_6_~I .input_register_mode = "none";
+defparam \inst|d_hsync_state_out_6_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_state_out_6_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_state_out_6_~I .oe_power_up = "low";
+defparam \inst|d_hsync_state_out_6_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_state_out_6_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_state_out_6_~I .operation_mode = "output";
+defparam \inst|d_hsync_state_out_6_~I .output_async_reset = "none";
+defparam \inst|d_hsync_state_out_6_~I .output_power_up = "low";
+defparam \inst|d_hsync_state_out_6_~I .output_register_mode = "none";
+defparam \inst|d_hsync_state_out_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L25
+stratix_io \inst|d_line_counter_out_8_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_8 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[8]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_8_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_8_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_8_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_8_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_8_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_8_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_8_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_8_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_8_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_8_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_8_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_8_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_8_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_8_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L24
+stratix_io \inst|d_line_counter_out_7_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_7 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[7]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_7_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_7_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_7_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_7_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_7_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_7_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_7_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_7_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_7_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_7_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_7_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_7_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_7_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_7_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M5
+stratix_io \inst|d_line_counter_out_6_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_6 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_6_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_6_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_6_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_6_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_6_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_6_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_6_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_6_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_6_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_6_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_6_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_6_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_6_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M6
+stratix_io \inst|d_line_counter_out_5_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_5 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_5_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_5_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_5_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_5_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_5_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_5_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_5_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_5_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_5_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_5_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_5_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_5_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_5_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M8
+stratix_io \inst|d_line_counter_out_4_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_4 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_4_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_4_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_4_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_4_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_4_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_4_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_4_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_4_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_4_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_4_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_4_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_4_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_4_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M9
+stratix_io \inst|d_line_counter_out_3_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_3 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_3_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_3_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_3_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_3_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_3_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_3_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_3_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_3_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_3_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_3_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_3_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_3_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_3_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_J22
+stratix_io \inst|d_line_counter_out_2_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_2 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_2_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_2_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_2_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_2_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_2_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_2_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_2_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_2_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_2_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_2_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_2_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_2_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_2_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K4
+stratix_io \inst|d_line_counter_out_1_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_1_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_1_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_1_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_1_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_1_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_1_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_1_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_1_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_1_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_1_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_1_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_1_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_1_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K6
+stratix_io \inst|d_line_counter_out_0_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_0_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_0_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_0_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_0_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_0_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_0_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_0_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_0_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_0_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_0_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_0_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_0_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_0_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_T19
+stratix_io \inst|d_toggle_counter_out_24_~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[24]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_24_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_24_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_24_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_24_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_24_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_24_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_24_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_24_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_24_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_24_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_24_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_24_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_24_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_24_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F23
+stratix_io \inst|d_toggle_counter_out_23_~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[23]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_23_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_23_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_23_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_23_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_23_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_23_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_23_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_23_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_23_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_23_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_23_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_23_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_23_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_23_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F25
+stratix_io \inst|d_toggle_counter_out_22_~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[22]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_22_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_22_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_22_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_22_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_22_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_22_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_22_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_22_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_22_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_22_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_22_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_22_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_22_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_22_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G1
+stratix_io \inst|d_toggle_counter_out_21_~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[21]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_21_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_21_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_21_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_21_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_21_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_21_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_21_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_21_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_21_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_21_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_21_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_21_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_21_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_21_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G3
+stratix_io \inst|d_toggle_counter_out_20_~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[20]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_20_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_20_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_20_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_20_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_20_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_20_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_20_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_20_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_20_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_20_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_20_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_20_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_20_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_20_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G5
+stratix_io \inst|d_toggle_counter_out_19_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_19 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[19]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_19_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_19_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_19_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_19_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_19_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_19_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_19_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_19_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_19_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_19_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_19_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_19_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_19_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_19_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G20
+stratix_io \inst|d_toggle_counter_out_18_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_18 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[18]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_18_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_18_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_18_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_18_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_18_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_18_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_18_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_18_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_18_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_18_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_18_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_18_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_18_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_18_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G21
+stratix_io \inst|d_toggle_counter_out_17_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_17 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[17]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_17_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_17_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_17_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_17_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_17_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_17_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_17_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_17_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_17_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_17_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_17_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_17_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_17_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_17_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G23
+stratix_io \inst|d_toggle_counter_out_16_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_16 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[16]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_16_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_16_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_16_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_16_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_16_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_16_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_16_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_16_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_16_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_16_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_16_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_16_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_16_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_16_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G24
+stratix_io \inst|d_toggle_counter_out_15_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_15 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[15]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_15_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_15_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_15_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_15_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_15_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_15_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_15_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_15_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_15_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_15_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_15_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_15_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_15_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_15_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F13
+stratix_io \inst|d_toggle_counter_out_14_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_14 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[14]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_14_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_14_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_14_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_14_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_14_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_14_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_14_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_14_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_14_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_14_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_14_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_14_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_14_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_14_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_E16
+stratix_io \inst|d_toggle_counter_out_13_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_13 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[13]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_13_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_13_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_13_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_13_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_13_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_13_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_13_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_13_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_13_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_13_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_13_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_13_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_13_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_13_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_E14
+stratix_io \inst|d_toggle_counter_out_12_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_12 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[12]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_12_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_12_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_12_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_12_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_12_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_12_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_12_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_12_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_12_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_12_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_12_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_12_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_12_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_12_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_D24
+stratix_io \inst|d_toggle_counter_out_11_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_11 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[11]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_11_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_11_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_11_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_11_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_11_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_11_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_11_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_11_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_11_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_11_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_11_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_11_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_11_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_11_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F12
+stratix_io \inst|d_toggle_counter_out_10_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_10 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[10]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_10_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_10_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_10_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_10_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_10_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_10_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_10_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_10_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_10_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_10_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_10_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_10_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_10_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_10_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_C16
+stratix_io \inst|d_toggle_counter_out_9_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_9 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[9]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_9_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_9_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_9_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_9_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_9_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_9_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_9_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_9_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_9_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_9_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_9_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_9_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_9_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_9_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H16
+stratix_io \inst|d_toggle_counter_out_8_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_8 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[8]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_8_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_8_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_8_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_8_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_8_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_8_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_8_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_8_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_8_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_8_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_8_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_8_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_8_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_8_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_AA16
+stratix_io \inst|d_toggle_counter_out_7_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_7 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[7]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_7_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_7_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_7_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_7_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_7_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_7_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_7_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_7_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_7_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_7_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_7_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_7_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_7_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_7_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F15
+stratix_io \inst|d_toggle_counter_out_6_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_6 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_6_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_6_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_6_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_6_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_6_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_6_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_6_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_6_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_6_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_6_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_6_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_6_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_6_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_C15
+stratix_io \inst|d_toggle_counter_out_5_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_5 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_5_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_5_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_5_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_5_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_5_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_5_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_5_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_5_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_5_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_5_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_5_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_5_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_5_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_Y16
+stratix_io \inst|d_toggle_counter_out_4_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_4 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_4_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_4_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_4_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_4_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_4_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_4_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_4_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_4_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_4_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_4_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_4_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_4_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_4_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_E13
+stratix_io \inst|d_toggle_counter_out_3_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_3 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_3_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_3_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_3_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_3_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_3_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_3_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_3_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_3_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_3_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_3_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_3_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_3_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_3_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_B16
+stratix_io \inst|d_toggle_counter_out_2_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_2 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_2_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_2_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_2_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_2_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_2_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_2_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_2_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_2_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_2_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_2_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_2_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_2_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_2_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_C25
+stratix_io \inst|d_toggle_counter_out_1_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_1_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_1_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_1_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_1_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_1_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_1_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_1_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_1_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_1_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_1_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_1_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_1_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_1_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H26
+stratix_io \inst|d_toggle_counter_out_0_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_0_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_0_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_0_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_0_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_0_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_0_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_0_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_0_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_0_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_0_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_0_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_0_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_0_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G2
+stratix_io \inst|d_vsync_counter_out_9_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_9 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[9]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_9_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_9_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_9_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_9_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_9_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_9_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_9_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_9_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_9_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_9_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_9_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_9_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_9_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_9_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G4
+stratix_io \inst|d_vsync_counter_out_8_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_8 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[8]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_8_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_8_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_8_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_8_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_8_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_8_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_8_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_8_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_8_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_8_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_8_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_8_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_8_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_8_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G6
+stratix_io \inst|d_vsync_counter_out_7_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_7 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[7]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_7_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_7_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_7_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_7_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_7_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_7_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_7_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_7_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_7_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_7_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_7_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_7_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_7_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_7_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_A10
+stratix_io \inst|d_vsync_counter_out_6_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_6 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_6_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_6_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_6_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_6_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_6_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_6_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_6_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_6_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_6_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_6_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_6_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_6_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_6_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_D11
+stratix_io \inst|d_vsync_counter_out_5_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_5 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_5_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_5_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_5_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_5_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_5_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_5_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_5_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_5_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_5_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_5_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_5_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_5_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_5_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H2
+stratix_io \inst|d_vsync_counter_out_4_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_4 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_4_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_4_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_4_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_4_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_4_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_4_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_4_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_4_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_4_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_4_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_4_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_4_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_4_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G10
+stratix_io \inst|d_vsync_counter_out_3_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_3 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_3_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_3_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_3_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_3_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_3_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_3_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_3_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_3_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_3_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_3_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_3_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_3_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_3_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_C11
+stratix_io \inst|d_vsync_counter_out_2_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_2 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_2_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_2_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_2_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_2_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_2_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_2_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_2_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_2_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_2_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_2_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_2_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_2_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_2_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H10
+stratix_io \inst|d_vsync_counter_out_1_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_1_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_1_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_1_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_1_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_1_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_1_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_1_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_1_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_1_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_1_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_1_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_1_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_1_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G9
+stratix_io \inst|d_vsync_counter_out_0_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_0_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_0_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_0_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_0_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_0_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_0_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_0_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_0_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_0_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_0_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_0_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_0_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_0_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F5
+stratix_io \inst|d_vsync_state_out_0_~I (
+ .datain(\inst|vga_driver_unit|vsync_state_0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_state[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_state_out_0_~I .ddio_mode = "none";
+defparam \inst|d_vsync_state_out_0_~I .input_async_reset = "none";
+defparam \inst|d_vsync_state_out_0_~I .input_power_up = "low";
+defparam \inst|d_vsync_state_out_0_~I .input_register_mode = "none";
+defparam \inst|d_vsync_state_out_0_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_state_out_0_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_state_out_0_~I .oe_power_up = "low";
+defparam \inst|d_vsync_state_out_0_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_state_out_0_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_state_out_0_~I .operation_mode = "output";
+defparam \inst|d_vsync_state_out_0_~I .output_async_reset = "none";
+defparam \inst|d_vsync_state_out_0_~I .output_power_up = "low";
+defparam \inst|d_vsync_state_out_0_~I .output_register_mode = "none";
+defparam \inst|d_vsync_state_out_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F4
+stratix_io \inst|d_vsync_state_out_1_~I (
+ .datain(\inst|vga_driver_unit|vsync_state_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_state[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_state_out_1_~I .ddio_mode = "none";
+defparam \inst|d_vsync_state_out_1_~I .input_async_reset = "none";
+defparam \inst|d_vsync_state_out_1_~I .input_power_up = "low";
+defparam \inst|d_vsync_state_out_1_~I .input_register_mode = "none";
+defparam \inst|d_vsync_state_out_1_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_state_out_1_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_state_out_1_~I .oe_power_up = "low";
+defparam \inst|d_vsync_state_out_1_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_state_out_1_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_state_out_1_~I .operation_mode = "output";
+defparam \inst|d_vsync_state_out_1_~I .output_async_reset = "none";
+defparam \inst|d_vsync_state_out_1_~I .output_power_up = "low";
+defparam \inst|d_vsync_state_out_1_~I .output_register_mode = "none";
+defparam \inst|d_vsync_state_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F3
+stratix_io \inst|d_vsync_state_out_2_~I (
+ .datain(\inst|vga_driver_unit|vsync_state_2 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_state[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_state_out_2_~I .ddio_mode = "none";
+defparam \inst|d_vsync_state_out_2_~I .input_async_reset = "none";
+defparam \inst|d_vsync_state_out_2_~I .input_power_up = "low";
+defparam \inst|d_vsync_state_out_2_~I .input_register_mode = "none";
+defparam \inst|d_vsync_state_out_2_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_state_out_2_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_state_out_2_~I .oe_power_up = "low";
+defparam \inst|d_vsync_state_out_2_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_state_out_2_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_state_out_2_~I .operation_mode = "output";
+defparam \inst|d_vsync_state_out_2_~I .output_async_reset = "none";
+defparam \inst|d_vsync_state_out_2_~I .output_power_up = "low";
+defparam \inst|d_vsync_state_out_2_~I .output_register_mode = "none";
+defparam \inst|d_vsync_state_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M19
+stratix_io \inst|d_vsync_state_out_3_~I (
+ .datain(\inst|vga_driver_unit|vsync_state_3 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_state[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_state_out_3_~I .ddio_mode = "none";
+defparam \inst|d_vsync_state_out_3_~I .input_async_reset = "none";
+defparam \inst|d_vsync_state_out_3_~I .input_power_up = "low";
+defparam \inst|d_vsync_state_out_3_~I .input_register_mode = "none";
+defparam \inst|d_vsync_state_out_3_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_state_out_3_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_state_out_3_~I .oe_power_up = "low";
+defparam \inst|d_vsync_state_out_3_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_state_out_3_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_state_out_3_~I .operation_mode = "output";
+defparam \inst|d_vsync_state_out_3_~I .output_async_reset = "none";
+defparam \inst|d_vsync_state_out_3_~I .output_power_up = "low";
+defparam \inst|d_vsync_state_out_3_~I .output_register_mode = "none";
+defparam \inst|d_vsync_state_out_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M18
+stratix_io \inst|d_vsync_state_out_4_~I (
+ .datain(\inst|vga_driver_unit|vsync_state_4 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_state[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_state_out_4_~I .ddio_mode = "none";
+defparam \inst|d_vsync_state_out_4_~I .input_async_reset = "none";
+defparam \inst|d_vsync_state_out_4_~I .input_power_up = "low";
+defparam \inst|d_vsync_state_out_4_~I .input_register_mode = "none";
+defparam \inst|d_vsync_state_out_4_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_state_out_4_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_state_out_4_~I .oe_power_up = "low";
+defparam \inst|d_vsync_state_out_4_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_state_out_4_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_state_out_4_~I .operation_mode = "output";
+defparam \inst|d_vsync_state_out_4_~I .output_async_reset = "none";
+defparam \inst|d_vsync_state_out_4_~I .output_power_up = "low";
+defparam \inst|d_vsync_state_out_4_~I .output_register_mode = "none";
+defparam \inst|d_vsync_state_out_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M7
+stratix_io \inst|d_vsync_state_out_5_~I (
+ .datain(\inst|vga_driver_unit|vsync_state_5 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_state[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_state_out_5_~I .ddio_mode = "none";
+defparam \inst|d_vsync_state_out_5_~I .input_async_reset = "none";
+defparam \inst|d_vsync_state_out_5_~I .input_power_up = "low";
+defparam \inst|d_vsync_state_out_5_~I .input_register_mode = "none";
+defparam \inst|d_vsync_state_out_5_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_state_out_5_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_state_out_5_~I .oe_power_up = "low";
+defparam \inst|d_vsync_state_out_5_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_state_out_5_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_state_out_5_~I .operation_mode = "output";
+defparam \inst|d_vsync_state_out_5_~I .output_async_reset = "none";
+defparam \inst|d_vsync_state_out_5_~I .output_power_up = "low";
+defparam \inst|d_vsync_state_out_5_~I .output_register_mode = "none";
+defparam \inst|d_vsync_state_out_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M4
+stratix_io \inst|d_vsync_state_out_6_~I (
+ .datain(\inst|vga_driver_unit|vsync_state_6 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_state[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_state_out_6_~I .ddio_mode = "none";
+defparam \inst|d_vsync_state_out_6_~I .input_async_reset = "none";
+defparam \inst|d_vsync_state_out_6_~I .input_power_up = "low";
+defparam \inst|d_vsync_state_out_6_~I .input_register_mode = "none";
+defparam \inst|d_vsync_state_out_6_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_state_out_6_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_state_out_6_~I .oe_power_up = "low";
+defparam \inst|d_vsync_state_out_6_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_state_out_6_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_state_out_6_~I .operation_mode = "output";
+defparam \inst|d_vsync_state_out_6_~I .output_async_reset = "none";
+defparam \inst|d_vsync_state_out_6_~I .output_power_up = "low";
+defparam \inst|d_vsync_state_out_6_~I .output_register_mode = "none";
+defparam \inst|d_vsync_state_out_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_T2
+stratix_io \inst|seven_seg_pin_tri_13_~I (
+ .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[13]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_tri_13_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_tri_13_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_tri_13_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_tri_13_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_tri_13_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_AA11
+stratix_io \inst|seven_seg_pin_out_12_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[12]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_12_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_12_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_12_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_12_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_12_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_12_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_12_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_12_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_12_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_12_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_12_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_12_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_12_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_12_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R6
+stratix_io \inst|seven_seg_pin_out_11_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[11]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_11_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_11_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_11_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_11_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_11_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_11_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_11_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_11_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_11_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_11_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_11_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_11_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_11_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_11_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R4
+stratix_io \inst|seven_seg_pin_out_10_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[10]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_10_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_10_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_10_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_10_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_10_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_10_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_10_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_10_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_10_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_10_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_10_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_10_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_10_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_10_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_N8
+stratix_io \inst|seven_seg_pin_out_9_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[9]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_9_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_9_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_9_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_9_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_9_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_9_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_9_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_9_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_9_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_9_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_9_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_9_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_9_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_9_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_N7
+stratix_io \inst|seven_seg_pin_out_8_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[8]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_8_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_8_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_8_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_8_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_8_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_8_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_8_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_8_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_8_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_8_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_8_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_8_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_8_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_8_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_Y11
+stratix_io \inst|seven_seg_pin_out_7_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[7]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_7_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_7_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_7_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_7_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_7_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_7_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_7_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_7_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_7_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_7_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_7_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_7_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_7_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_7_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R23
+stratix_io \inst|seven_seg_pin_tri_6_~I (
+ .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_tri_6_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_tri_6_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_tri_6_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_tri_6_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_tri_6_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R22
+stratix_io \inst|seven_seg_pin_tri_5_~I (
+ .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_tri_5_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_tri_5_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_tri_5_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_tri_5_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_tri_5_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R21
+stratix_io \inst|seven_seg_pin_tri_4_~I (
+ .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_tri_4_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_tri_4_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_tri_4_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_tri_4_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_tri_4_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R20
+stratix_io \inst|seven_seg_pin_tri_3_~I (
+ .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_tri_3_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_tri_3_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_tri_3_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_tri_3_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_tri_3_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R19
+stratix_io \inst|seven_seg_pin_out_2_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_2_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_2_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_2_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_2_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_2_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_2_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_2_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_2_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_2_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_2_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_2_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_2_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_2_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R9
+stratix_io \inst|seven_seg_pin_out_1_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_1_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_1_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_1_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_1_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_1_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_1_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_1_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_1_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_1_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_1_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_1_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_1_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_1_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R8
+stratix_io \inst|seven_seg_pin_tri_0_~I (
+ .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_tri_0_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_tri_0_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_tri_0_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_tri_0_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_tri_0_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+endmodule
projects / dide_16.git / blobdiff