--- /dev/null
+
+BeginView vga NoName
+Inst: dly_counter[1] dly_counter_1_ stratix_lcell_ff
+Inst: dly_counter[0] dly_counter_0_ stratix_lcell_ff
+Inst: d_vsync_state_out[0] d_vsync_state_out_0_ stratix_io
+Inst: d_vsync_state_out[1] d_vsync_state_out_1_ stratix_io
+Inst: d_vsync_state_out[2] d_vsync_state_out_2_ stratix_io
+Inst: d_vsync_state_out[3] d_vsync_state_out_3_ stratix_io
+Inst: d_vsync_state_out[4] d_vsync_state_out_4_ stratix_io
+Inst: d_vsync_state_out[5] d_vsync_state_out_5_ stratix_io
+Inst: d_vsync_state_out[6] d_vsync_state_out_6_ stratix_io
+Inst: d_hsync_state_out[0] d_hsync_state_out_0_ stratix_io
+Inst: d_hsync_state_out[1] d_hsync_state_out_1_ stratix_io
+Inst: d_hsync_state_out[2] d_hsync_state_out_2_ stratix_io
+Inst: d_hsync_state_out[3] d_hsync_state_out_3_ stratix_io
+Inst: d_hsync_state_out[4] d_hsync_state_out_4_ stratix_io
+Inst: d_hsync_state_out[5] d_hsync_state_out_5_ stratix_io
+Inst: d_hsync_state_out[6] d_hsync_state_out_6_ stratix_io
+Inst: d_vsync_counter_out[9] d_vsync_counter_out_9_ stratix_io
+Inst: d_vsync_counter_out[8] d_vsync_counter_out_8_ stratix_io
+Inst: d_vsync_counter_out[7] d_vsync_counter_out_7_ stratix_io
+Inst: d_vsync_counter_out[6] d_vsync_counter_out_6_ stratix_io
+Inst: d_vsync_counter_out[5] d_vsync_counter_out_5_ stratix_io
+Inst: d_vsync_counter_out[4] d_vsync_counter_out_4_ stratix_io
+Inst: d_vsync_counter_out[3] d_vsync_counter_out_3_ stratix_io
+Inst: d_vsync_counter_out[2] d_vsync_counter_out_2_ stratix_io
+Inst: d_vsync_counter_out[1] d_vsync_counter_out_1_ stratix_io
+Inst: d_vsync_counter_out[0] d_vsync_counter_out_0_ stratix_io
+Inst: d_hsync_counter_out[9] d_hsync_counter_out_9_ stratix_io
+Inst: d_hsync_counter_out[8] d_hsync_counter_out_8_ stratix_io
+Inst: d_hsync_counter_out[7] d_hsync_counter_out_7_ stratix_io
+Inst: d_hsync_counter_out[6] d_hsync_counter_out_6_ stratix_io
+Inst: d_hsync_counter_out[5] d_hsync_counter_out_5_ stratix_io
+Inst: d_hsync_counter_out[4] d_hsync_counter_out_4_ stratix_io
+Inst: d_hsync_counter_out[3] d_hsync_counter_out_3_ stratix_io
+Inst: d_hsync_counter_out[2] d_hsync_counter_out_2_ stratix_io
+Inst: d_hsync_counter_out[1] d_hsync_counter_out_1_ stratix_io
+Inst: d_hsync_counter_out[0] d_hsync_counter_out_0_ stratix_io
+Inst: d_line_counter_out[8] d_line_counter_out_8_ stratix_io
+Inst: d_line_counter_out[7] d_line_counter_out_7_ stratix_io
+Inst: d_line_counter_out[6] d_line_counter_out_6_ stratix_io
+Inst: d_line_counter_out[5] d_line_counter_out_5_ stratix_io
+Inst: d_line_counter_out[4] d_line_counter_out_4_ stratix_io
+Inst: d_line_counter_out[3] d_line_counter_out_3_ stratix_io
+Inst: d_line_counter_out[2] d_line_counter_out_2_ stratix_io
+Inst: d_line_counter_out[1] d_line_counter_out_1_ stratix_io
+Inst: d_line_counter_out[0] d_line_counter_out_0_ stratix_io
+Inst: d_column_counter_out[9] d_column_counter_out_9_ stratix_io
+Inst: d_column_counter_out[8] d_column_counter_out_8_ stratix_io
+Inst: d_column_counter_out[7] d_column_counter_out_7_ stratix_io
+Inst: d_column_counter_out[6] d_column_counter_out_6_ stratix_io
+Inst: d_column_counter_out[5] d_column_counter_out_5_ stratix_io
+Inst: d_column_counter_out[4] d_column_counter_out_4_ stratix_io
+Inst: d_column_counter_out[3] d_column_counter_out_3_ stratix_io
+Inst: d_column_counter_out[2] d_column_counter_out_2_ stratix_io
+Inst: d_column_counter_out[1] d_column_counter_out_1_ stratix_io
+Inst: d_column_counter_out[0] d_column_counter_out_0_ stratix_io
+Inst: seven_seg_pin_tri[13] seven_seg_pin_tri_13_ stratix_io
+Inst: seven_seg_pin_out[12] seven_seg_pin_out_12_ stratix_io
+Inst: seven_seg_pin_out[11] seven_seg_pin_out_11_ stratix_io
+Inst: seven_seg_pin_out[10] seven_seg_pin_out_10_ stratix_io
+Inst: seven_seg_pin_out[9] seven_seg_pin_out_9_ stratix_io
+Inst: seven_seg_pin_out[8] seven_seg_pin_out_8_ stratix_io
+Inst: seven_seg_pin_out[7] seven_seg_pin_out_7_ stratix_io
+Inst: seven_seg_pin_tri[6] seven_seg_pin_tri_6_ stratix_io
+Inst: seven_seg_pin_tri[5] seven_seg_pin_tri_5_ stratix_io
+Inst: seven_seg_pin_tri[4] seven_seg_pin_tri_4_ stratix_io
+Inst: seven_seg_pin_tri[3] seven_seg_pin_tri_3_ stratix_io
+Inst: seven_seg_pin_out[2] seven_seg_pin_out_2_ stratix_io
+Inst: seven_seg_pin_out[1] seven_seg_pin_out_1_ stratix_io
+Inst: seven_seg_pin_tri[0] seven_seg_pin_tri_0_ stratix_io
+Net: vga_driver_unit.COLUMN_COUNT_next\.un10_column_counter_siglt6_1 vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_1
+Net: vga_driver_unit.COLUMN_COUNT_next\.un10_column_counter_siglt6_3 vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_3
+Net: DELAY_RESET_next\.un6_dly_counter_0_x DELAY_RESET_next_un6_dly_counter_0_x
+Net: vga_driver_unit.h_sync vga_driver_unit_h_sync
+Net: vga_driver_unit.v_sync vga_driver_unit_v_sync
+Net: vga_driver_unit.column_counter_sig[0] vga_driver_unit_column_counter_sig[0]
+Net: vga_driver_unit.column_counter_sig[1] vga_driver_unit_column_counter_sig[1]
+Net: vga_driver_unit.column_counter_sig[2] vga_driver_unit_column_counter_sig[2]
+Net: vga_driver_unit.column_counter_sig[3] vga_driver_unit_column_counter_sig[3]
+Net: vga_driver_unit.column_counter_sig[4] vga_driver_unit_column_counter_sig[4]
+Net: vga_driver_unit.column_counter_sig[5] vga_driver_unit_column_counter_sig[5]
+Net: vga_driver_unit.column_counter_sig[6] vga_driver_unit_column_counter_sig[6]
+Net: vga_driver_unit.column_counter_sig[7] vga_driver_unit_column_counter_sig[7]
+Net: vga_driver_unit.column_counter_sig[8] vga_driver_unit_column_counter_sig[8]
+Net: vga_driver_unit.column_counter_sig[9] vga_driver_unit_column_counter_sig[9]
+Net: vga_driver_unit.line_counter_sig[0] vga_driver_unit_line_counter_sig[0]
+Net: vga_driver_unit.line_counter_sig[1] vga_driver_unit_line_counter_sig[1]
+Net: vga_driver_unit.line_counter_sig[2] vga_driver_unit_line_counter_sig[2]
+Net: vga_driver_unit.line_counter_sig[3] vga_driver_unit_line_counter_sig[3]
+Net: vga_driver_unit.line_counter_sig[4] vga_driver_unit_line_counter_sig[4]
+Net: vga_driver_unit.line_counter_sig[5] vga_driver_unit_line_counter_sig[5]
+Net: vga_driver_unit.line_counter_sig[6] vga_driver_unit_line_counter_sig[6]
+Net: vga_driver_unit.line_counter_sig[7] vga_driver_unit_line_counter_sig[7]
+Net: vga_driver_unit.line_counter_sig[8] vga_driver_unit_line_counter_sig[8]
+Net: vga_driver_unit.hsync_counter[0] vga_driver_unit_hsync_counter[0]
+Net: vga_driver_unit.hsync_counter[1] vga_driver_unit_hsync_counter[1]
+Net: vga_driver_unit.hsync_counter[2] vga_driver_unit_hsync_counter[2]
+Net: vga_driver_unit.hsync_counter[3] vga_driver_unit_hsync_counter[3]
+Net: vga_driver_unit.hsync_counter[4] vga_driver_unit_hsync_counter[4]
+Net: vga_driver_unit.hsync_counter[5] vga_driver_unit_hsync_counter[5]
+Net: vga_driver_unit.hsync_counter[6] vga_driver_unit_hsync_counter[6]
+Net: vga_driver_unit.hsync_counter[7] vga_driver_unit_hsync_counter[7]
+Net: vga_driver_unit.hsync_counter[8] vga_driver_unit_hsync_counter[8]
+Net: vga_driver_unit.hsync_counter[9] vga_driver_unit_hsync_counter[9]
+Net: vga_driver_unit.vsync_counter[0] vga_driver_unit_vsync_counter[0]
+Net: vga_driver_unit.vsync_counter[1] vga_driver_unit_vsync_counter[1]
+Net: vga_driver_unit.vsync_counter[2] vga_driver_unit_vsync_counter[2]
+Net: vga_driver_unit.vsync_counter[3] vga_driver_unit_vsync_counter[3]
+Net: vga_driver_unit.vsync_counter[4] vga_driver_unit_vsync_counter[4]
+Net: vga_driver_unit.vsync_counter[5] vga_driver_unit_vsync_counter[5]
+Net: vga_driver_unit.vsync_counter[6] vga_driver_unit_vsync_counter[6]
+Net: vga_driver_unit.vsync_counter[7] vga_driver_unit_vsync_counter[7]
+Net: vga_driver_unit.vsync_counter[8] vga_driver_unit_vsync_counter[8]
+Net: vga_driver_unit.vsync_counter[9] vga_driver_unit_vsync_counter[9]
+Net: vga_driver_unit.d_set_hsync_counter vga_driver_unit_d_set_hsync_counter
+Net: vga_driver_unit.d_set_vsync_counter vga_driver_unit_d_set_vsync_counter
+Net: vga_driver_unit.h_enable_sig vga_driver_unit_h_enable_sig
+Net: vga_driver_unit.v_enable_sig vga_driver_unit_v_enable_sig
+Net: vga_control_unit.r vga_control_unit_r
+Net: vga_control_unit.g vga_control_unit_g
+Net: vga_control_unit.b vga_control_unit_b
+Net: vga_driver_unit.hsync_state[6] vga_driver_unit_hsync_state[6]
+Net: vga_driver_unit.hsync_state[5] vga_driver_unit_hsync_state[5]
+Net: vga_driver_unit.hsync_state[4] vga_driver_unit_hsync_state[4]
+Net: vga_driver_unit.hsync_state[3] vga_driver_unit_hsync_state[3]
+Net: vga_driver_unit.hsync_state[2] vga_driver_unit_hsync_state[2]
+Net: vga_driver_unit.hsync_state[1] vga_driver_unit_hsync_state[1]
+Net: vga_driver_unit.hsync_state[0] vga_driver_unit_hsync_state[0]
+Net: vga_driver_unit.vsync_state[6] vga_driver_unit_vsync_state[6]
+Net: vga_driver_unit.vsync_state[5] vga_driver_unit_vsync_state[5]
+Net: vga_driver_unit.vsync_state[4] vga_driver_unit_vsync_state[4]
+Net: vga_driver_unit.vsync_state[3] vga_driver_unit_vsync_state[3]
+Net: vga_driver_unit.vsync_state[2] vga_driver_unit_vsync_state[2]
+Net: vga_driver_unit.vsync_state[1] vga_driver_unit_vsync_state[1]
+Net: vga_driver_unit.vsync_state[0] vga_driver_unit_vsync_state[0]
+Net: clk_pin_c G_49
+EndView vga NoName
+
+BeginView vga_driver NoName
+Inst: hsync_counter[0] hsync_counter_0_ stratix_lcell_ff
+Inst: hsync_counter[1] hsync_counter_1_ stratix_lcell_ff
+Inst: hsync_counter[2] hsync_counter_2_ stratix_lcell_ff
+Inst: hsync_counter[3] hsync_counter_3_ stratix_lcell_ff
+Inst: hsync_counter[4] hsync_counter_4_ stratix_lcell_ff
+Inst: hsync_counter[5] hsync_counter_5_ stratix_lcell_ff
+Inst: hsync_counter[6] hsync_counter_6_ stratix_lcell_ff
+Inst: hsync_counter[7] hsync_counter_7_ stratix_lcell_ff
+Inst: hsync_counter[8] hsync_counter_8_ stratix_lcell_ff
+Inst: hsync_counter[9] hsync_counter_9_ stratix_lcell_ff
+Inst: vsync_counter[0] vsync_counter_0_ stratix_lcell_ff
+Inst: vsync_counter[1] vsync_counter_1_ stratix_lcell_ff
+Inst: vsync_counter[2] vsync_counter_2_ stratix_lcell_ff
+Inst: vsync_counter[3] vsync_counter_3_ stratix_lcell_ff
+Inst: vsync_counter[4] vsync_counter_4_ stratix_lcell_ff
+Inst: vsync_counter[5] vsync_counter_5_ stratix_lcell_ff
+Inst: vsync_counter[6] vsync_counter_6_ stratix_lcell_ff
+Inst: vsync_counter[7] vsync_counter_7_ stratix_lcell_ff
+Inst: vsync_counter[8] vsync_counter_8_ stratix_lcell_ff
+Inst: vsync_counter[9] vsync_counter_9_ stratix_lcell_ff
+Inst: column_counter_sig[9] column_counter_sig_9_ stratix_lcell_ff
+Inst: column_counter_sig[8] column_counter_sig_8_ stratix_lcell_ff
+Inst: column_counter_sig[7] column_counter_sig_7_ stratix_lcell_ff
+Inst: column_counter_sig[6] column_counter_sig_6_ stratix_lcell_ff
+Inst: column_counter_sig[5] column_counter_sig_5_ stratix_lcell_ff
+Inst: column_counter_sig[4] column_counter_sig_4_ stratix_lcell_ff
+Inst: column_counter_sig[3] column_counter_sig_3_ stratix_lcell_ff
+Inst: column_counter_sig[2] column_counter_sig_2_ stratix_lcell_ff
+Inst: column_counter_sig[1] column_counter_sig_1_ stratix_lcell_ff
+Inst: column_counter_sig[0] column_counter_sig_0_ stratix_lcell_ff
+Inst: hsync_state[6] hsync_state_6_ stratix_lcell_ff
+Inst: vsync_state[0] vsync_state_0_ stratix_lcell_ff
+Inst: vsync_state[1] vsync_state_1_ stratix_lcell_ff
+Inst: vsync_state[6] vsync_state_6_ stratix_lcell_ff
+Inst: line_counter_sig[8] line_counter_sig_8_ stratix_lcell_ff
+Inst: line_counter_sig[7] line_counter_sig_7_ stratix_lcell_ff
+Inst: line_counter_sig[6] line_counter_sig_6_ stratix_lcell_ff
+Inst: line_counter_sig[5] line_counter_sig_5_ stratix_lcell_ff
+Inst: line_counter_sig[4] line_counter_sig_4_ stratix_lcell_ff
+Inst: line_counter_sig[3] line_counter_sig_3_ stratix_lcell_ff
+Inst: line_counter_sig[2] line_counter_sig_2_ stratix_lcell_ff
+Inst: line_counter_sig[1] line_counter_sig_1_ stratix_lcell_ff
+Inst: line_counter_sig[0] line_counter_sig_0_ stratix_lcell_ff
+Inst: v_enable_sig v_enable_sig_Z stratix_lcell_ff
+Inst: h_enable_sig h_enable_sig_Z stratix_lcell_ff
+Inst: h_sync h_sync_Z stratix_lcell_ff
+Inst: v_sync v_sync_Z stratix_lcell_ff
+Inst: vsync_state[5] vsync_state_5_ stratix_lcell_ff
+Inst: vsync_state[4] vsync_state_4_ stratix_lcell_ff
+Inst: vsync_state[3] vsync_state_3_ stratix_lcell_ff
+Inst: vsync_state[2] vsync_state_2_ stratix_lcell_ff
+Inst: hsync_state[5] hsync_state_5_ stratix_lcell_ff
+Inst: hsync_state[4] hsync_state_4_ stratix_lcell_ff
+Inst: hsync_state[3] hsync_state_3_ stratix_lcell_ff
+Inst: hsync_state[2] hsync_state_2_ stratix_lcell_ff
+Inst: hsync_state[1] hsync_state_1_ stratix_lcell_ff
+Inst: hsync_state[0] hsync_state_0_ stratix_lcell_ff
+Inst: vsync_state_next_2_sqmuxa vsync_state_next_2_sqmuxa_cZ stratix_lcell
+Inst: hsync_state_3_0_0_0__g0_0 hsync_state_3_0_0_0__g0_0_cZ stratix_lcell
+Inst: un1_hsync_state_next_1_sqmuxa_0 un1_hsync_state_next_1_sqmuxa_0_cZ stratix_lcell
+Inst: un1_vsync_state_next_1_sqmuxa_0 un1_vsync_state_next_1_sqmuxa_0_cZ stratix_lcell
+Inst: COLUMN_COUNT_next\.un10_column_counter_siglto9 COLUMN_COUNT_next_un10_column_counter_siglto9 stratix_lcell
+Inst: vsync_state_3_iv_0_0__g0_0_a3_0 vsync_state_3_iv_0_0__g0_0_a3_0_cZ stratix_lcell
+Inst: LINE_COUNT_next\.un10_line_counter_siglto8 LINE_COUNT_next_un10_line_counter_siglto8 stratix_lcell
+Inst: vsync_state_next_1_sqmuxa_1 vsync_state_next_1_sqmuxa_1_cZ stratix_lcell
+Inst: vsync_state_next_1_sqmuxa_2 vsync_state_next_1_sqmuxa_2_cZ stratix_lcell
+Inst: vsync_state_next_1_sqmuxa_3 vsync_state_next_1_sqmuxa_3_cZ stratix_lcell
+Inst: hsync_state_next_1_sqmuxa_2 hsync_state_next_1_sqmuxa_2_cZ stratix_lcell
+Inst: hsync_state_next_1_sqmuxa_1 hsync_state_next_1_sqmuxa_1_cZ stratix_lcell
+Inst: VSYNC_COUNT_next\.un9_vsync_counterlt9 VSYNC_COUNT_next_un9_vsync_counterlt9 stratix_lcell
+Inst: COLUMN_COUNT_next\.un10_column_counter_siglt6 COLUMN_COUNT_next_un10_column_counter_siglt6 stratix_lcell
+Inst: HSYNC_FSM_next\.un12_hsync_counter HSYNC_FSM_next_un12_hsync_counter stratix_lcell
+Inst: HSYNC_FSM_next\.un13_hsync_counter HSYNC_FSM_next_un13_hsync_counter stratix_lcell
+Inst: HSYNC_COUNT_next\.un9_hsync_counterlt9 HSYNC_COUNT_next_un9_hsync_counterlt9 stratix_lcell
+Inst: LINE_COUNT_next\.un10_line_counter_siglto5 LINE_COUNT_next_un10_line_counter_siglto5 stratix_lcell
+Inst: VSYNC_FSM_next\.un13_vsync_counter_4 VSYNC_FSM_next_un13_vsync_counter_4 stratix_lcell
+Inst: VSYNC_FSM_next\.un15_vsync_counter_4 VSYNC_FSM_next_un15_vsync_counter_4 stratix_lcell
+Inst: line_counter_next_0_sqmuxa_1_1 line_counter_next_0_sqmuxa_1_1_cZ stratix_lcell
+Inst: v_sync_1_0_0_0_g1 v_sync_1_0_0_0_g1_cZ stratix_lcell
+Inst: h_enable_sig_1_0_0_0_g0_i_o4 h_enable_sig_1_0_0_0_g0_i_o4_cZ stratix_lcell
+Inst: vsync_counter_next_1_sqmuxa vsync_counter_next_1_sqmuxa_cZ stratix_lcell
+Inst: VSYNC_FSM_next\.un14_vsync_counter_8 VSYNC_FSM_next_un14_vsync_counter_8 stratix_lcell
+Inst: hsync_counter_next_1_sqmuxa hsync_counter_next_1_sqmuxa_cZ stratix_lcell
+Inst: column_counter_next_0_sqmuxa_1_1 column_counter_next_0_sqmuxa_1_1_cZ stratix_lcell
+Inst: h_sync_1_0_0_0_g1 h_sync_1_0_0_0_g1_cZ stratix_lcell
+Inst: v_enable_sig_1_0_0_0_g0_i_o4 v_enable_sig_1_0_0_0_g0_i_o4_cZ stratix_lcell
+Inst: HSYNC_FSM_next\.un12_hsync_counter_4 HSYNC_FSM_next_un12_hsync_counter_4 stratix_lcell
+Inst: HSYNC_FSM_next\.un12_hsync_counter_3 HSYNC_FSM_next_un12_hsync_counter_3 stratix_lcell
+Inst: HSYNC_FSM_next\.un11_hsync_counter_3 HSYNC_FSM_next_un11_hsync_counter_3 stratix_lcell
+Inst: HSYNC_FSM_next\.un11_hsync_counter_2 HSYNC_FSM_next_un11_hsync_counter_2 stratix_lcell
+Inst: HSYNC_COUNT_next\.un9_hsync_counterlt9_3 HSYNC_COUNT_next_un9_hsync_counterlt9_3 stratix_lcell
+Inst: HSYNC_FSM_next\.un13_hsync_counter_2 HSYNC_FSM_next_un13_hsync_counter_2 stratix_lcell
+Inst: VSYNC_COUNT_next\.un9_vsync_counterlt9_6 VSYNC_COUNT_next_un9_vsync_counterlt9_6 stratix_lcell
+Inst: VSYNC_COUNT_next\.un9_vsync_counterlt9_5 VSYNC_COUNT_next_un9_vsync_counterlt9_5 stratix_lcell
+Inst: VSYNC_FSM_next\.un13_vsync_counter_3 VSYNC_FSM_next_un13_vsync_counter_3 stratix_lcell
+Inst: VSYNC_FSM_next\.un15_vsync_counter_3 VSYNC_FSM_next_un15_vsync_counter_3 stratix_lcell
+Inst: HSYNC_FSM_next\.un10_hsync_counter_4 HSYNC_FSM_next_un10_hsync_counter_4 stratix_lcell
+Inst: HSYNC_FSM_next\.un10_hsync_counter_3 HSYNC_FSM_next_un10_hsync_counter_3 stratix_lcell
+Inst: LINE_COUNT_next\.un10_line_counter_siglt4_2 LINE_COUNT_next_un10_line_counter_siglt4_2 stratix_lcell
+Inst: VSYNC_FSM_next\.un12_vsync_counter_6 VSYNC_FSM_next_un12_vsync_counter_6 stratix_lcell
+Inst: VSYNC_FSM_next\.un12_vsync_counter_7 VSYNC_FSM_next_un12_vsync_counter_7 stratix_lcell
+Inst: COLUMN_COUNT_next\.un10_column_counter_siglt6_1 COLUMN_COUNT_next_un10_column_counter_siglt6_1 stratix_lcell
+Inst: HSYNC_FSM_next\.un13_hsync_counter_7 HSYNC_FSM_next_un13_hsync_counter_7 stratix_lcell
+Inst: HSYNC_FSM_next\.un10_hsync_counter_1 HSYNC_FSM_next_un10_hsync_counter_1 stratix_lcell
+Inst: un1_hsync_state_3_0 un1_hsync_state_3_0_cZ stratix_lcell
+Inst: un1_vsync_state_2_0 un1_vsync_state_2_0_cZ stratix_lcell
+Inst: d_set_vsync_counter d_set_vsync_counter_cZ stratix_lcell
+Inst: COLUMN_COUNT_next\.un10_column_counter_siglt6_3 COLUMN_COUNT_next_un10_column_counter_siglt6_3 stratix_lcell
+Inst: d_set_hsync_counter d_set_hsync_counter_cZ stratix_lcell
+Inst: un1_line_counter_sig[9] un1_line_counter_sig_9_ stratix_lcell
+Inst: un1_line_counter_sig[8] un1_line_counter_sig_8_ stratix_lcell
+Inst: un1_line_counter_sig[7] un1_line_counter_sig_7_ stratix_lcell
+Inst: un1_line_counter_sig[6] un1_line_counter_sig_6_ stratix_lcell
+Inst: un1_line_counter_sig[5] un1_line_counter_sig_5_ stratix_lcell
+Inst: un1_line_counter_sig[4] un1_line_counter_sig_4_ stratix_lcell
+Inst: un1_line_counter_sig[3] un1_line_counter_sig_3_ stratix_lcell
+Inst: un1_line_counter_sig[2] un1_line_counter_sig_2_ stratix_lcell
+Inst: un1_line_counter_sig_a[1] un1_line_counter_sig_a_1_ stratix_lcell
+Inst: un1_line_counter_sig[1] un1_line_counter_sig_1_ stratix_lcell
+Inst: un2_column_counter_next[9] un2_column_counter_next_9_ stratix_lcell
+Inst: un2_column_counter_next[8] un2_column_counter_next_8_ stratix_lcell
+Inst: un2_column_counter_next[7] un2_column_counter_next_7_ stratix_lcell
+Inst: un2_column_counter_next[6] un2_column_counter_next_6_ stratix_lcell
+Inst: un2_column_counter_next[5] un2_column_counter_next_5_ stratix_lcell
+Inst: un2_column_counter_next[4] un2_column_counter_next_4_ stratix_lcell
+Inst: un2_column_counter_next[3] un2_column_counter_next_3_ stratix_lcell
+Inst: un2_column_counter_next[2] un2_column_counter_next_2_ stratix_lcell
+Inst: un2_column_counter_next[1] un2_column_counter_next_1_ stratix_lcell
+Inst: un2_column_counter_next[0] un2_column_counter_next_0_ stratix_lcell
+Inst: line_counter_next_0_sqmuxa_1_1_i line_counter_next_0_sqmuxa_1_1_i_cZ inv
+Inst: column_counter_next_0_sqmuxa_1_1_i column_counter_next_0_sqmuxa_1_1_i_cZ inv
+Inst: un9_vsync_counterlt9_i un9_vsync_counterlt9_i_cZ inv
+Inst: G_16_i_i G_16_i_i_cZ inv
+Inst: un9_hsync_counterlt9_i un9_hsync_counterlt9_i_cZ inv
+Inst: G_2_i_i G_2_i_i_cZ inv
+EndView vga_driver NoName
+
+BeginView vga_control NoName
+Inst: b b_Z stratix_lcell_ff
+Inst: r r_Z stratix_lcell_ff
+Inst: g g_Z stratix_lcell_ff
+Inst: N_23_i_0_g0_a N_23_i_0_g0_a_cZ stratix_lcell
+Inst: N_4_i_0_g0_1 N_4_i_0_g0_1_cZ stratix_lcell
+Inst: N_6_i_0_g0_0 N_6_i_0_g0_0_cZ stratix_lcell
+Inst: b_next_i_a7_1 b_next_i_a7_1_cZ stratix_lcell
+Inst: b_next_i_o3_0 b_next_i_o3_0_cZ stratix_lcell
+Inst: r_next_i_o7 r_next_i_o7_cZ stratix_lcell
+Inst: g_next_i_o3 g_next_i_o3_cZ stratix_lcell
+EndView vga_control NoName
projects / dide_16.git / blobdiff