--- /dev/null
+%%% protect protected_file
+@E
+@
+#
+#
+#
+# Created by Synplify VHDL Compiler version comp400rc, Build 020R from Synplicity, Inc.
+# Copyright 1994-2009 Synopsys, Inc. , All rights reserved.
+# Synthesis Netlist written on Thu Oct 29 16:49:28 2009
+#
+#
+#OPTIONS:"|-top|vga|-infer_seqShift|-primux|-fixsmult|-dspmac|-nram|-divnmod|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|on|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"/opt/synplify/fpga_c200906/linux/c_vhdl":1242928055
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/location.map":1242864830
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":1242776237
+#CUR:"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd":1256830367
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/std1164.vhd":1242776237
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/unsigned.vhd":1242776237
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/arith.vhd":1242776237
+#CUR:"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_ent.vhd":1255952276
+#CUR:"/homes/burban/didelu/dide_16/bsp3/Designflow/src/board_driver_ent.vhd":1255952276
+#CUR:"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_ent.vhd":1256830136
+#CUR:"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_ent.vhd":1255952276
+#CUR:"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_arc.vhd":1255952276
+#CUR:"/homes/burban/didelu/dide_16/bsp3/Designflow/src/board_driver_arc.vhd":1255952276
+#CUR:"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_arc.vhd":1256831362
+#CUR:"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_arc.vhd":1255952276
+f "/opt/synplify/fpga_c200906/lib/vhd/std.vhd"; # file 0
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd"; # file 1
+af .is_vhdl 1;
+f "/opt/synplify/fpga_c200906/lib/vhd/std1164.vhd"; # file 2
+af .is_vhdl 1;
+f "/opt/synplify/fpga_c200906/lib/vhd/unsigned.vhd"; # file 3
+af .is_vhdl 1;
+f "/opt/synplify/fpga_c200906/lib/vhd/arith.vhd"; # file 4
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_ent.vhd"; # file 5
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp3/Designflow/src/board_driver_ent.vhd"; # file 6
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_ent.vhd"; # file 7
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_ent.vhd"; # file 8
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_arc.vhd"; # file 9
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp3/Designflow/src/board_driver_arc.vhd"; # file 10
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_arc.vhd"; # file 11
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_arc.vhd"; # file 12
+af .is_vhdl 1;
+@E
+@
+ftell;
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+PHR3#8PED;R4
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+RNH3Ds0_HFsolMNC#R"CMPC_o#C"b;
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+-y---------------------------------
+
+@
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+NRs3FHNohl"CRP_oN8PsHC;s"
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+4;
+@HR@dU:U::(dgU:R ODR OD;H
+NR03sDs_FHNoMl"CRO"D ;
+
+
+
+@HR@dU:g::(d4g:4CRs#RC0sCC#0N;
+HsR30FD_sMHoNRlC"#sCC;0"
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+HsR30FD_sMHoNRlC"MDHCF_OkCM0s
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+RNH3Ds0_HFsolMNCER"_NCML"DC;
+
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+
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+RNH3Ds0_HFsolMNCPR"#O$M"
+;
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+HsR30FD_sMHoNRlC"E8_#O$M_kOFMs0C"
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+HsR30FD_sMHoNRlC"P8_#O$M_kOFMs0C"
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+HsR30FD_sMHoNRlC"#8_CP0_#O$M_kOFMs0C"
+;
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+@FR@6U:.::(6..:n_R8#_C0OkFDlOM_F0kMC8sR_0#C_DOFk_lMOMFk0;Cs
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projects / dide_16.git / blobdiff