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4er slot (3. bsp fertig)
[dide_16.git] / bsp3 / Designflow / syn / rev_1 / syntmp / vga_flink.htm
diff --git a/bsp3/Designflow/syn/rev_1/syntmp/vga_flink.htm b/bsp3/Designflow/syn/rev_1/syntmp/vga_flink.htm
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index 0000000..1ee3bfe
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+++ b/bsp3/Designflow/syn/rev_1/syntmp/vga_flink.htm
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+<table border="0" cellpadding="0" cellspacing="2">
+<tr>
+<td nowrap class="content" valign="top">
+<body bgcolor="#e0e0ff">
+<font size=3><b>Log File Links:</b><br></font>
+<br><b>rev_1</b><br>
+<dt><a href="/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/rpt_vga.areasrr:@XP_FILE" target="srrFrame">Hierarchical Area Report (/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/rpt_vga)</a> (16:49 29-Oct)</dt><br>
+<br><br><a href="/homes/burban/stdout.log:@XP_FILE" target="srrFrame">Session Log</a><br>
dide laboruebung (ws09)