4er slot (3. bsp fertig)

[dide_16.git] / bsp3 / Designflow / syn / rev_1 / syntmp / vga.plg

diff --git a/bsp3/Designflow/syn/rev_1/syntmp/vga.plg b/bsp3/Designflow/syn/rev_1/syntmp/vga.plg
new file mode 100644 (file)
index 0000000..8aafcd6
--- /dev/null
+++ b/bsp3/Designflow/syn/rev_1/syntmp/vga.plg
@@ -0,0 +1,13 @@
+@P:  Part : EP1S25FC672-6
+@P:  Worst Slack : 34.836
+@P:  vga|clk_pin - Estimated Frequency : 204.7 MHz
+@P:  vga|clk_pin - Requested Frequency : 25.2 MHz
+@P:  vga|clk_pin - Estimated Period : 4.886
+@P:  vga|clk_pin - Requested Period : 39.722
+@P:  vga|clk_pin - Slack : 34.836
+@P: vga Part : ep1s25fc672-6
+@P: vga I/O ATOMs : 91
+@P: vga Total LUTs: : 141 of 25660 ( 0%)
+@P: vga Logic resources : 143 ATOMs of 25660 ( 0%)
+@P: vga DSP Blocks : 0 (0 nine-bit DSP elements)
+@P:  CPU Time : 0h:00m:04s